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| 6/20/03 powerpc 405gp embedded processor data sheet page 1 of 60 features ? ibm powerpc ? 405 32-bit risc processor core operating up to 266mhz ? synchronous dram (sdram) interface operating up to 133mhz - 32-bit interface for non-ecc applications - 40-bit interface serves 32 bits of data plus 8 check bits for ecc applications ? 4kb on-chip memory (ocm) ? external peripheral bus - flash rom/boot rom interface - direct support for 8-, 16-, or 32-bit sram and external peripherals - up to eight devices - external mastering supported ? dma support for external peripherals, internal uart and memory - scatter-gather chaining supported - four channels ? pci revision 2.2 compliant interface (32-bit, up to 66mhz) - synchronous or asynchronous pci bus interface - internal or external pci bus arbiter ? ethernet 10/100mbps (full-duplex) support with media independent interface (mii) ? programmable interrupt controller supports seven external and 19 internal edge triggered or level-sensitive interrupts ? programmable timers ? two serial ports (16550 compatible uart) ? one iic interface ? general purpose i/o (gpio) available ? supports jtag for board level testing ? internal processor local bus (plb) runs at sdram interface frequency ? supports powerpc processor boot from pci memory description designed specifically to address embedded applications, the powerpc 405gp (ppc405gp) provides a high-performance, low-power solution that interfaces to a wide range of peripherals by incorporating on-chip power management features and lower power dissipation requirements. this chip contains a high-performance risc processor core, sdram controller, pci bus interface, ethernet interface, control for external rom and peripherals, dma with scatter-gather support, serial ports, iic interface, and general purpose i/o. technology: ibm cmos sa-12e, 0.25 m (0.18 m l eff ) package: 456-ball (35mm or 27mm), or 413-ball (25mm) enhanced plastic ball grid array (e-pbga) power (typical): tbdw at 133mhz, 1.5w at 200mhz, 2w at 266mhz .com .com .com 4 .com u datasheet
powerpc 405gp embedded processor data sheet page 2 of 60 6/20/03 contents ordering, pvr, and jtag information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 address map support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 on-chip memory (ocm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 plb to pci interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 sdram memory controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 external peripheral bus controller (ebc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 dma controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 iic bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 general purpose io (gpio) controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 universal interrupt controller (uic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 10/100 mbps ethernet mac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 jtag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 signal list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 spread spectrum clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 strapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 tables system memory address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 dcr address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 signals listed alphabetically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 signals listed by ball assignment413-ball package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 signals listed by ball assignment456-ball package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 pin summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 signal functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 package thermal specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 recommended dc operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 input capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 clocking specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 peripheral interface clock timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 i/o specificationsall speeds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 i/o specifications133 and 200mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 i/o specifications266mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 ppc405gp strapping pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 .com .com .com .com 4 .com u datasheet powerpc 405gp embedded processor data sheet 6/20/03 page 3 of 60 figures ppc405gp embedded controller functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 25mm, 413-ball e-pbga package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 27mm, 456-ball e-pbga package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 35mm, 456-ball e-pbga package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5v-tolerant input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 input setup and hold waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 output delay and float timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 .com .com .com .com 4 .com u datasheet powerpc 405gp embedded processor data sheet page 4 of 60 6/20/03 ordering, pvr, and jtag information this section provides the part number nomenclature. for availability, contact your local ibm sales office. the part number contains a part modifier. included in the modifier is a revision code. this refers to the die mask revision number and is specified in the part numbering scheme for identification purposes only. the pvr (processor version register) is software accessible and contains additional information about the revision level of the part. refer to the powerpc 405gp embedded processor users manual for details on the register content. order part number key product name order part number 1 processor frequency package rev level pvr value jtag id ppc405gp IBM25PPC405GP-3be133c 133mhz 35mm, 456 e-pbga e 0x40110145 0x42050049 ppc405gp IBM25PPC405GP3be133cz 133mhz 35mm, 456 e-pbga e 0x40110145 0x42050049 ppc405gp IBM25PPC405GP-3de133c 133mhz 27mm, 456 e-pbga e 0x40110145 0x42050049 ppc405gp IBM25PPC405GP-3de133cz 133mhz 27mm, 456 e-pbga e 0x40110145 0x42050049 ppc405gp IBM25PPC405GP-3be200c 200mhz 35mm, 456 e-pbga e 0x40110145 0x42050049 ppc405gp IBM25PPC405GP3be200cz 200mhz 35mm, 456 e-pbga e 0x40110145 0x42050049 ppc405gp IBM25PPC405GP-3de200c 200mhz 27mm, 456 e-pbga e 0x40110145 0x42050049 ppc405gp IBM25PPC405GP-3de200cz 200mhz 27mm, 456 e-pbga e 0x40110145 0x42050049 ppc405gp IBM25PPC405GP-3ee200c 200mhz 25mm, 413 e-pbga e 0x40110145 0x42050049 ppc405gp IBM25PPC405GP-3ee200cz 200mhz 25mm, 413 e-pbga e 0x40110145 0x42050049 ppc405gp IBM25PPC405GP-3be266c 266mhz 35mm, 456 e-pbga e 0x40110145 0x42050049 ppc405gp IBM25PPC405GP-3be266cz 266mhz 35mm, 456 e-pbga e 0x40110145 0x42050049 ppc405gp IBM25PPC405GP-3de266c 266mhz 27mm, 456 e-pbga e 0x40110145 0x42050049 ppc405gp IBM25PPC405GP-3de266cz 266mhz 27mm, 456 e-pbga e 0x40110145 0x42050049 ppc405gp IBM25PPC405GP-3ee266c 266mhz 25mm, 413 e-pbga e 0x40110145 0x42050049 ppc405gp IBM25PPC405GP-3ee266cz 266mhz 25mm, 413 e-pbga e 0x40110145 0x42050049 note 1: z at the end of the order part number indicates a tape and reel shipping package. otherwise, the chips are shipped in a tray. ibm part number IBM25PPC405GP-3be200cx package processor speed grade 3 reliability operational case temperature revision level shipping package blank = tray z = tape and reel (-40c to +85c) range 200 mhz 266 mhz b: 35mm, 456 e-pbga d: 27mm, 456 e-pbga e: 25mm, 413 e-pbga 133 mhz .com .com .com .com 4 .com u datasheet powerpc 405gp embedded processor data sheet 6/20/03 page 5 of 60 ppc405gp embedded controller functional block diagram the ppc405gp is designed using the ibm microelectronics blue logic tm methodology in which major functional blocks are integrated together to create an application-specific asic product. this approach provides a consistent way to create complex asics using ibm coreconnect tm bus architecture. ppc405 processor core docm iocm dcu icu ocm control ocm sram dcr bus 16kb on-chip peripheral bus (opb) gpio iic uart uart mal ethernet dma bridge processor local bus (plb) sdram pci bridge code decompression external bus controller controller clock control reset power mgmt jtag trace timers mmu mii controller opb interrupt controller arb 32-bit addr 32-bit data 13-bit addr 32-bit data external bus master controller universal i-cache d-cache (4-channel) (codepack ? ) 66 mhz max (async) dcrs 33 mhz max (sync) 8kb arb .com .com .com .com 4 .com u datasheet powerpc 405gp embedded processor data sheet page 6 of 60 6/20/03 address map support the ppc405gp incorporates two simple and separate address maps. the first address map defines the possible use of address regions that the processor can access. the second address map is for device configuration registers (dcrs). the dcrs are accessed by software running on the ppc405gp processor through the use of mtdcr and mfdcr instructions. system memory address map 4gb system memory function subfunction start address end address size general use sdram, external peripherals, and pci memory note: any of the address ranges listed at right may be use for any of the above functions. 0x00000000 0xe7ffffff 3712mb 0xe8010000 0xe87fffff 8mb 0xec000000 0xeebfffff 44mb 0xeee00000 0xef3fffff 6mb 0xef500000 0xef5fffff 1mb 0xf0000000 0xffffffff 256mb boot-up peripheral bus boot 1 0xffe00000 0xffffffff 2mb pci boot 2 0xfffe0000 0xffffffff 128kb pci pci i/o 0xe8000000 0xe800ffff 64kb pci i/o 0xe8800000 0xebffffff 56mb configuration registers 0xeec00000 0xeec00007 8b interrupt acknowledge and special cycle 0xeed00000 0xeed00003 4b local configuration registers 0xef400000 0xef40003f 64b internal peripherals uart0 0xef600300 0xef600307 8b uart1 0xef600400 0xef600407 8b iic0 0xef600500 0xef60051f 32b opb arbiter 0xef600600 0xef60063f 64b gpio controller registers 0xef600700 0xef60077f 128b ethernet controller registers 0xef600800 0xef6008ff 256b notes: 1. when peripheral bus boot is selected, peripheral bank 0 is automatically configured at reset to the address range listed abov e. 2. if pci boot is selected, a plb-to-pci mapping is automatically configured at reset to the address range listed above. 3. after the boot process, software may reassign the boot memory regions for other uses. 4. all address ranges not listed above are reserved. .com .com .com .com 4 .com u datasheet powerpc 405gp embedded processor data sheet 6/20/03 page 7 of 60 dcr address map 4kb device configuration registers function start address end address size total dcr address space 1 0x000 0x3ff 1kw (4kb) 1 by function: reserved 0x000 0x00f 16w memory controller registers 0x010 0x011 2w external bus controller registers 0x012 0x013 2w decompression controller registers 0x014 0x015 2w reserved 0x016 0x017 2w on-chip memory controller registers 0x018 0x01f 8w reserved 0x020 0x07f 96w plb registers 0x080 0x08f 16w reserved 0x090 0x09f 16w opb bridge out registers 0x0a0 0x0a7 8w reserved 0x0a8 0x0af 6w clock, control, and reset 0x0b0 0x0b7 8w power management 0x0b8 0x0bf 8w interrupt controller 0x0c0 0x0cf 16w reserved 0x0d0 0x0ff 48w dma controller registers 0x100 0x13f 64w reserved 0x140 0x17f 64w ethernet mal registers 0x180 0x1ff 128w reserved 0x200 0x3ff 512w notes: 1. dcr address space is addressable with up to 10 bits (1024 or 1k unique addresses). each unique address represents a single 32-bit (word) register, or 1 kiloword (kw) (which equals 4 kb). .com .com .com .com 4 .com u datasheet powerpc 405gp embedded processor data sheet page 8 of 60 6/20/03 on-chip memory (ocm) the ocm feature comprises a memory controller and a one-port 4kb static ram (sram) accessed by the processor core. features include: ? low-latency access to critical instructions and data ? performance identical to cache hits without misses ? contents change only under program control plb to pci interface the plb to pci interface core provides a mechanism for connecting pci devices to the local powerpc processor and local memory. this interface is compliant with version 2.2 of the pci specification. features include: ? internal pci bus arbiter for up to six external devices at pci bus speeds up to 66mhz. internal arbiter use is optional and can be disabled for systems which employ an external arbiter. ? pci bus frequency up to 66mhz - synchronous operation at 1/n fractions of plb speed (n = 1 to 4) to 33mhz maximum - asynchronous operation from 1/8 plb frequency to 66mhz maximum ? 32-bit pci address/data bus ? power management: - pci bus power management v1.1 compliant ? supports 1:1, 2:1, 3:1, 4:1 clock ratios from plb to pci ? buffering between plb and pci: - pci target 64-byte write post buffer - pci target 96-byte read prefetch buffer - plb slave 32-byte write post buffer - plb slave 64-byte read prefetch buffer ? error tracking/status ? supports pci target side configuration ? supports processor access to all pci address spaces: - single-byte pci i/o reads and writes - pci memory single-beat and prefetch-burst reads and single-beat writes - single-byte pci configuration reads and writes (type 0 and type 1) .com .com .com .com 4 .com u datasheet powerpc 405gp embedded processor data sheet 6/20/03 page 9 of 60 - pci interrupt acknowledge - pci special cycle ? supports pci target access to all plb address spaces ? supports powerpc processor boot from pci memory sdram memory controller the ppc405gp memory controller core provides a low latency access path to sdram memory. a variety of system memory configurations are supported. the memory controller supports up to four physical banks. up to 256mb per bank are supported, up to a maximum of 1gb. memory timings, address and bank sizes, and memory addressing modes are programmable. features include: ? 11x8 to 13x11 addressing for sdram (2- and 4-bank) ? 32-bit memory interface support ? programmable address compare for each bank of memory ? industry standard 168-pin dimms are supported (some configurations) ? 4mb to 256mb per bank ? programmable address mapping and timing ? auto refresh ? page mode accesses with up to 4 open pages ? power management (self-refresh) ? error checking and correction (ecc) support - standard single-error correct, double-error detect coverage - aligned nibble error detect - address error logging external peripheral bus controller (ebc) ? supports eight banks of rom, eprom, sram, flash memory, or slave peripherals ? burst and non-burst devices ? 8-, 16-, 32-bit byte-addressable data bus width support ? latch data on ready ? programmable 2k clock time-out counter with disable for ready .com .com .com .com 4 .com u datasheet powerpc 405gp embedded processor data sheet page 10 of 60 6/20/03 ? programmable access timing per device - 0C255 wait states for non-bursting devices - 0C31 burst wait states for first access and up to 7 wait states for subsequent accesses - programmable cson, csoff relative to address - programmable oeon, weon, weoff (0 to 3 clock cycles) relative to cs ? programmable address mapping ? peripheral device pacing with external ready ? external master interface - write posting from external master - read prefetching on plb for external master reads - bursting capable from external master - allows external master access to all non-ebc plb slaves - external master can control ebc slaves for own access and control dma controller ? supports the following transfers: - memory-to-memory transfers - buffered peripheral to memory transfers - buffered memory to peripheral transfers ? four channels ? scatter/gather capability for programming multiple dma operations ? 8-, 16-, 32-bit peripheral support (opb and external) ? 32-bit addressing ? address increment or decrement ? internal 32-byte data buffering capability ? supports internal and external peripherals ? support for memory mapped peripherals ? support for peripherals running on slower frequency buses .com .com .com .com 4 .com u datasheet powerpc 405gp embedded processor data sheet 6/20/03 page 11 of 60 serial interface ? one 8-pin uart and one 4-pin uart interface provided ? selectable internal or external serial clock to allow a wide range of baud rates ? register compatibility with ns16550 register set ? complete status reporting capability ? transmitter and receiver are each buffered with 16-byte fifos when in fifo mode ? fully programmable serial-interface characteristics ? supports dma using internal dma engine iic bus interface ? compliant with philips? semiconductors i 2 c specification, dated 1995 ? operation at 100khz or 400khz ? 8-bit data ? 10- or 7-bit address ? slave transmitter and receiver ? master transmitter and receiver ? multiple bus masters ? supports fixed v dd iic interface ? two independent 4 x 1 byte data buffers ? twelve memory-mapped, fully programmable configuration registers ? one programmable interrupt request signal ? provides full management of all iic bus protocol ? programmable error recovery .com .com .com .com 4 .com u datasheet powerpc 405gp embedded processor data sheet page 12 of 60 6/20/03 general purpose io (gpio) controller ? controller functions and gpio registers are programmed and accessed via memory-mapped opb bus master accesses ? 23 gpios are pin-shared with other functions. dcrs control whether a particular pin that has gpio capabilities acts as a gpio or is used for another purpose. the 23 gpios are multiplexed with: - 7 of 8 chip selects - all seven external interrupts - all nine instruction trace pins ? each gpio output is separately programmable to emulate an open-drain driver (i.e., drives to zero, three- stated if output bit is 1) universal interrupt controller (uic) the universal interrupt controller (uic) provides the control, status, and communications necessary between the various sources of interrupts and the local powerpc processor. features include: ? supports seven external and 19 internal interrupts ? edge triggered or level-sensitive ? positive or negative active ? non-critical or critical interrupt to processor core ? programmable critical interrupt priority ordering ? programmable critical interrupt vector for faster vector processing 10/100 mbps ethernet mac ? capable of handling full/half duplex 100mbps and 10mbps operation ? uses the medium independent interface (mii) to the physical layer (phy not included on chip) jtag ? ieee 1149.1 test access port ? ibm riscwatch debugger support ? jtag boundary scan description language (bsdl) .com .com .com .com 4 .com u datasheet powerpc 405gp embedded processor data sheet 6/20/03 page 13 of 60 25mm, 413-ball e-pbga package a 1.00 ? 0.635 solder ball x 413 25.0 22.0 25.0 a b c 0.20 ? 0.30 ? 0.10 m c a b 15.7 max 0.20 c c 0.539 ref 0.5 0.1 typ glob top b c d e f g h j k l m aa n p r t u v w y ab ac 135 7 911131517 19 2 4 6 810 12 14 16 18 21 23 20 22 top view bottom view 0.35 c note: all dimensions are in mm. m a1 ball corner 0.25 c thermal balls 2.223 ref .com .com .com .com 4 .com u datasheet powerpc 405gp embedded processor data sheet page 14 of 60 6/20/03 27mm, 456-ball e-pbga package a s 1.00 ? 0.55 0.15 solderball x 456 26 af 27.0 25.0 27.0 a b c 0.20 ? 0.40 ? 0.20 s c a b s s 24.0 ref small radius corner corresponds to ejector mark 1.80 x 0.10 0.15 c c 2.21 0.45 b c d e f g h j k l m aa n p r t u v w y ab ac ad ae thermal balls a1 ball location 135 7 911131517 19 2 4 6 810 12 14 16 18 21 23 25 20 22 24 top view bottom view 0.35 c r 0.1 0 r 0.50 index mark 16.00 16.00 c 4.00 1.10 note: all dimensions are in mm. .com .com .com .com 4 .com u datasheet powerpc 405gp embedded processor data sheet 6/20/03 page 15 of 60 35mm, 456-ball e-pbga package a s 1.27 typ 0.65 0.05 solderball x 456 26 af 35.0 0.2 31.75 35.0 b a c 0.20 ? 0.30 ? 0.15 s c ab s s 33.5 ref 17.5 typ gold gate release corresponds to reserved area for ejector pin mark x 4 typ corner shape is chamferred or rounded 0.20 c c 2.49 ref 0.6 0.1 pcb substrate mold compound b c d e f g h j k l m aa n p r t u v w y ab ac ad ae thermal balls a1 ball location 135 7 911131517 19 2 4 6 810 12 14 16 18 21 23 25 20 22 24 top view bottom view 0.25 0.35 c c note: all dimensions are in mm. 2.65 max .com .com .com .com 4 .com u datasheet powerpc 405gp embedded processor data sheet page 16 of 60 6/20/03 pin lists the ppc405gp embedded controller is available as a 456-ball or a 413-ball e-pbga package. the 456-ball package is available in two sizes35 millimeters and 27 millimeters. the 413-ball package size is 25 millimeters. in this section there are three tables that correlate the external signals to the physical package pin (ball) on which they appear. the following table lists all the external signals in alphabetical order and shows the ball number on which the signal appears. multiplexed signals are shown with the default signal (following reset) not in brackets and the alternate signal in brackets. multiplexed signals appear alphabetically multiple times in the listonce for each signal name on the ball. the page number listed gives the page in signal functional description on page 34 where the signals in the indicated interface group begin. signals listed alphabetically (part 1 of 10) signal name 413-ball 456-ball interface group page av dd l21 d25 system 39 ba0 ba1 n16 n17 ab24 ac24 sdram 36 banksel0 banksel1 banksel2 banksel3 ac19 ab17 ac17 ab14 ad17 af17 ae15 ac14 sdram 36 [b e0 ]pcic0 [b e1 ]pcic1 [b e2 ]pcic2 [b e3 ]pcic3 d16 c22 e23 p23 d19 f24 k24 r26 pci 34 busreq t1 r3 external master peripheral 38 cas r15 ab23 sdram 36 clken0 clken1 ab22 y20 ab25 ac25 sdram 36 dmaack0 dmaack1 dmaack2 dmaack3 a17 b14 a15 a8 d16 b15 b14 c12 external slave peripheral 36 dmareq0 dmareq1 dmareq2 dmareq3 c13 a16 b9 c6 c16 d14 c11 a7 external slave peripheral 36 dqm0 dqm1 dqm2 dqm3 u12 ac5 ac2 aa2 ac12 ac10 ac6 aa3 sdram 36 dqmcb ab13 ac15 sdram 36 drvrinh1 drvrinh2 h17 g17 e24 e23 system 39 ecc0 ecc1 ecc2 ecc3 ecc4 ecc5 ecc6 ecc7 aa12 ac15 ab12 ac14 ac12 ac10 ac9 ab11 ae14 af15 af14 ad13 af13 af12 ae13 ad12 sdram 36 emcmdclk j20 h24 ethernet 35 emcmdio[phymdio] t17 ad26 ethernet 35 .com .com .com .com 4 .com u datasheet powerpc 405gp embedded processor data sheet 6/20/03 page 17 of 60 emctxd0 emctxd1 emctxd2 emctxd3 f22 k21 j22 r23 j26 l25 l24 p25 ethernet 35 emctxenj21 k23 ethernet 35 emctxerr k20 k25 ethernet 35 eot0/tc0 eot1/tc1 eot2/tc2 eot3/tc3 c2 g4 u3 v3 f3 g2 v2 y1 external slave peripheral 36 extack u4 y3 external master peripheral 38 extreq v4 y4 external master peripheral 38 extreset r2 t3 external master peripheral 38 gnd a1 a6 a18 a23 c14 d14 f1 f23 j11 j13 k11-k13 l1 l4 l11-l13 m4 m11-m13 m20 n11-n13 n20 n23 p11-p13 r11 r13 v1 v23 y10 aa10 ac1 ac6 ac18 ac23 a1 a2 a6 a11 a16 a19 1 a21 a26 b2 b25 b26 c3 c24 d4 d23 e5 e9 e13 e14 e18 e22 f1 f26 h1 1 j5 j22 l1 l11-l16 l26 m11-m16 n5 n11-n16 n22 p5 p11-p16 p22 r11-r16 t1 t11-t16 t26 v5 v22 w26 1 aa1 aa26 ab5 ground notes: 1. reserved on 27mm package. gnd on 35mm package. 2. on the 456-ball packages, l11-l16, m11-m16, n11-n16, p11-p16, r11-r16, and t11-t16 are also thermal balls. 3. on the 413-ball package, j11, j13, k11-k13, l11-l13, m11-n13, n11-n13, p11-p13, r11, and r13 are also thermal balls. 41 signals listed alphabetically (part 2 of 10) signal name 413-ball 456-ball interface group page .com .com .com .com 4 .com u datasheet powerpc 405gp embedded processor data sheet page 18 of 60 6/20/03 gnd ab9 ab13 ab14 ab18 ab22 ac4 ac23 ad3 ad24 ae1 ae2 ae25 af1 af6 af8 1 af11 af16 af21 af25 af26 ground notes: 1. reserved on 27mm package. gnd on 35mm package. 2. on the 456-ball packages, l11-l16, m11-m16, n11-n16, p11-p16, r11-r16, and t11-t16 are also thermal balls. 3. on the 413-ball package, j11, j13, k11-k13, l11-l13, m11-n13, n11-n13, p11-p13, r11, and r13 are also thermal balls. 41 g nt [pcireq0 ] d15 c19 pci 34 gpio1[ts1e] gpio2[ts2e] gpio3[ts1o] gpio4[ts2o] gpio5[ts3] gpio6[ts4] gpio7[ts5] gpio8[ts6] gpio9[trcclk] a20 c19 a21 ab18 ac4 ab4 ac3 y6 t7 d18 c20 a22 af18 ac9 ae8 af5 ac7 ab3 system 39 [gpio10]percs1 [gpio11]percs2 [gpio12]percs3 [gpio13]percs4 [gpio14]percs5 [gpio15]percs6 [gpio16]percs7 h11 g8 d5 c7 d10 b6 c10 c4 c5 a4 b9 b10 a9 b11 system 39 [gpio17]irq0 [gpio18]irq1 [gpio19]irq2 [gpio20]irq3 [gpio21]irq4 [gpio22]irq5 [gpio23]irq6 u21 y23 r20 y22 w21 u20 aa22 v25 v23 w24 w25 y24 y25 aa24 system 39 halt aa23 ab26 system 39 holdack p4 u2 external master peripheral 38 holdpri p3 t2 external master peripheral 38 holdreq v2 v1 external master peripheral 38 iicscl ab3 ad6 internal peripheral 38 iicsda y7 ae7 internal peripheral 38 irq0[gpio17] irq1[gpio18] irq2[gpio19] irq3[gpio20] irq4[gpio21] irq5[gpio22] irq6[gpio23] u21 y23 r20 y22 w21 u20 aa22 v25 v23 w24 w25 y24 y25 aa24 interrupts 39 signals listed alphabetically (part 3 of 10) signal name 413-ball 456-ball interface group page .com .com .com .com 4 .com u datasheet powerpc 405gp embedded processor data sheet 6/20/03 page 19 of 60 memaddr0 memaddr1 memaddr2 memaddr3 memaddr4 memaddr5 memaddr6 memaddr7 memaddr8 memaddr9 memaddr10 memaddr11 memaddr12 aa21 ac22 aa20 ab21 aa19 ab20 ac21 y16 y15 ab19 ac20 aa16 aa15 ae22 ac21 ae21 ad21 af22 ae20 ac19 ae19 ad19 ac18 af19 ad18 ac17 sdram note: during a cas cycle memaddr0 is the least significant bit (lsb) on this bus. 36 memclkout0 memclkout1 w20 ab23 ac26 aa23 sdram 36 memdata0 memdata1 memdata2 memdata3 memdata4 memdata5 memdata6 memdata7 memdata8 memdata9 memdata10 memdata11 memdata12 memdata13 memdata14 memdata15 memdata16 memdata17 memdata18 memdata19 memdata20 memdata21 memdata22 memdata23 memdata24 memdata25 memdata26 memdata27 memdata28 memdata29 memdata30 memdata31 ac8 ab10 aa11 ac7 ab7 ab9 ab8 ab6 aa9 aa7 y9 aa6 y8 aa5 aa4 ab2 y4 t11 u11 r9 m9 aa3 ab1 y3 w3 y2 aa1 t4 r4 w2 y1 t3 ac13 ae12 ad11 ac11 af10 ae11 ad10 af9 ad9 ae9 ad8 af7 ac8 ad7 ae6 ae5 ae4 ad5 ad4 ac5 ad1 ab2 aa4 aa2 ab1 y2 w4 w2 w3 v4 w1 v3 sdram note: memdata0 is the most significant bit (msb) on this bus. 36 signals listed alphabetically (part 4 of 10) signal name 413-ball 456-ball interface group page .com .com .com .com 4 .com u datasheet powerpc 405gp embedded processor data sheet page 20 of 60 6/20/03 ov dd a11 d11 g10 g15 h9 h10 h14 h15 j7 j8 j10 j14 j16 j17 k3 k4 k8 k16 l23 n1 p8 p16 p20 p21 r7 r8 r10 r14 r16 r17 t9 t10 t14 t15 u9 u14 y13 ac13 b17 1 c13 1 e6 e7 e8 e19 e20 e21 f5 f22 g5 g22 h5 h22 k2 1 n24 1 p3 1 u25 1 w5 w22 y5 y22 aa5 aa22 ab6 ab7 ab8 ab19 ab20 ab21 ad14 1 ae10 1 output driver voltage note 1: reserved on 27mm package. ov dd on 35mm package. 41 signals listed alphabetically (part 5 of 10) signal name 413-ball 456-ball interface group page .com .com .com .com 4 .com u datasheet powerpc 405gp embedded processor data sheet 6/20/03 page 21 of 60 pciad0 pciad1 pciad2 pciad3 pciad4 pciad5 pciad6 pciad7 pciad8 pciad9 pciad10 pciad11 pciad12 pciad13 pciad14 pciad15 pciad16 pciad17 pciad18 pciad19 pciad20 pciad21 pciad22 pciad23 pciad24 pciad25 pciad26 pciad27 pciad28 pciad29 pciad30 pciad31 b17 b15 b16 b18 a19 c15 c17 c18 c20 d19 a22 b22 d20 h13 m15 d21 g22 h22 g23 l22 m21 j23 m22 k23 n22 m16 t23 p22 n21 u22 r22 v22 a17 b16 c17 a18 d17 c18 b18 a20 b21 a23 d21 b22 b23 c22 c26 f25 k26 l23 m25 m23 n25 m26 n26 p24 r24 r23 p23 r25 t24 u26 t25 v26 pci note : pciad31 is the most significant bit (msb) on this bus. 34 pcic0[be0 ] pcic1[be1 ] pcic2[be2 ] pcic3[be3 ] d16 c22 e23 p23 d19 f24 k24 r26 pci 34 pciclk d17 b20 pci 34 pcidevsel h20 h25 pci 34 pciframe h21 j24 pci 34 pcignt0 [req ] pcignt1 pcignt2 pcignt3 pcignt4 pcignt5 w23 u23 b23 d23 k22 h23 u23 t23 f23 h26 n23 m24 pci 34 pciidsel m23 p26 pci 34 pciint [perwe ] g13 c23 pci 34 pciirdy e22 j23 pci 34 pciparity e21 e26 pci 34 pciperr d22 g25 pci 34 pcireq0 [gnt ] pcireq1 pcireq2 pcireq3 pcireq4 pcireq5 d15 b21 b20 g16 f20 g21 c19 c21 b19 a24 g23 j25 pci 34 pcireset k14 b24 pci 34 pciserr g20 g24 pci 34 signals listed alphabetically (part 6 of 10) signal name 413-ball 456-ball interface group page .com .com .com .com 4 .com u datasheet powerpc 405gp embedded processor data sheet page 22 of 60 6/20/03 pcistop c23 h23 pci 34 pcitrdy f21 g26 pci 34 peraddr0 peraddr1 peraddr2 peraddr3 peraddr4 peraddr5 peraddr6 peraddr7 peraddr8 peraddr9 peraddr10 peraddr11 peraddr12 peraddr13 peraddr14 peraddr15 peraddr16 peraddr17 peraddr18 peraddr19 peraddr20 peraddr21 peraddr22 peraddr23 peraddr24 peraddr25 peraddr26 peraddr27 peraddr28 peraddr29 peraddr30 peraddr31 g7 j12 c11 c3 a2 c4 b3 d6 c5 b4 d7 a3 d8 d9 b5 a4 c8 c9 a5 b7 b8 a7 b10 b11 c12 a9 b12 a10 a12 a14 b13 g12 d5 a3 b4 b5 d6 b6 c6 d7 a5 b7 c7 d8 b8 c8 d9 a8 c9 d10 c10 a10 d11 b12 d13 d12 b13 a12 a13 c14 a14 a15 c15 d15 external slave peripheral note: peraddr0 is the most significant bit (msb) on this bus. 36 perblast d3 f2 external slave peripheral 36 perclk j9 e4 external master peripheral 38 percs0 percs1 [gpio10] percs2 [gpio11] percs3 [gpio12] percs4 [gpio13] percs5 [gpio14] percs6 [gpio15] percs7 [gpio16] g11 h11 g8 d5 c7 d10 b6 c10 b3 c4 c5 a4 b9 b10 a9 b11 external slave peripheral 36 signals listed alphabetically (part 7 of 10) signal name 413-ball 456-ball interface group page .com .com .com .com 4 .com u datasheet powerpc 405gp embedded processor data sheet 6/20/03 page 23 of 60 perdata0 perdata1 perdata2 perdata3 perdata4 perdata5 perdata6 perdata7 perdata8 perdata9 perdata10 perdata11 perdata12 perdata13 perdata14 perdata15 perdata16 perdata17 perdata18 perdata19 perdata20 perdata21 perdata22 perdata23 perdata24 perdata25 perdata26 perdata27 perdata28 perdata29 perdata30 perdata31 r3 w1 u2 t2 u1 p2 n2 m3 r1 m2 p1 m1 k1 j1 l2 m8 h1 k2 l3 g1 g2 j2 h2 f2 e1 j3 g3 d1 j4 f3 d2 h4 u4 u3 u1 t4 r2 p4 r4 p2 r1 p1 n3 n1 m1 n2 m3 m4 n4 m2 l3 l4 k1 l2 k3 j1 k4 j3 j2 j4 h3 g1 h2 h4 external slave peripheral note: perdata0 is the most significant bit (msb) on this bus. 36 pererr h8 b1 external master peripheral 38 peroe k10 c2 external slave peripheral 36 perpar0 perpar1 perpar2 perpar3 l7 f4 e3 c1 d3 g4 g3 e1 external slave peripheral 36 perready l8 e3 external slave peripheral 36 perr/w h7 c1 external slave peripheral 36 perwbe0 perwbe1 perwbe2 perwbe3 d4 b2 b1 e4 d2 e2 f4 d1 external slave peripheral 36 [perwe ]pciint g13 c23 external slave peripheral 36 phycol y21 aa25 ethernet 35 phycrs t20 w23 ethernet 35 phyrxclk aa18 af20 ethernet 35 [phymdio]emcmdio t17 ad26 ethernet 35 phyrxd0 phyrxd1 phyrxd2 phyrxd3 aa13 y19 y18 y17 ae23 af23 ac20 ad20 ethernet 35 phyrxdv r21 v24 ethernet 35 phyrxerr t22 u24 ethernet 35 phytxclk c21 e25 ethernet 35 signals listed alphabetically (part 8 of 10) signal name 413-ball 456-ball interface group page .com .com .com .com 4 .com u datasheet powerpc 405gp embedded processor data sheet page 24 of 60 6/20/03 ras r12 af24 sdram 36 rcvrinh l17 c25 system 39 [r eq ]pcignt0 w23 u23 pci 34 reserved b19 c16 d18 e2 h3 t21 v20 v21 w22 y5 1 aa8 ab5 a19 2 b17 3 c13 3 d20 h1 2 k2 3 n24 3 p3 3 u25 3 w26 2 y23 y26 af4 1 af8 2 ad14 3 ae10 3 other notes: 1. y5 (on the 413-ball package) and af4 must be tied to ov dd or gnd. all other reserved pins should be left unconnected. 2. reserved on 27mm package. gnd on 35mm package. 3. reserved on 27mm package. ov dd on 35mm package. 41 sysclk h16 a25 system 39 syserr p14 ad25 system 39 sysreset j15 d22 system 39 tck u16 ad22 jtag 39 tdi u13 ae24 jtag 39 tdo t13 ad23 jtag 39 testen e20 d26 system 39 tmrclk l16 d24 system 39 tms u17 ac22 jtag 39 [trcclk]gpio9 t7 ab3 system 39 trst t16 ae26 jtag 39 [ts1e]gpio1 [ts2e]gpio2 [ts1o]gpio3 [ts2o]gpio4 [ts3]gpio5 [ts4]gpio6 [ts5]gpio7 [ts6]gpio8 a20 c19 a21 ab18 ac4 ab4 ac3 y6 d18 c20 a22 af18 ac9 ae8 af5 ac7 trace 40 uart0_cts u7 ab4 internal peripheral 38 uart0_dcd aa17 ae18 internal peripheral 38 uart0_dsr p10 ae3 internal peripheral 38 uart0_dtr t8 af2 internal peripheral 38 uart0_ri ac16 ad15 internal peripheral 38 uart0_rts ab15 ad16 internal peripheral 38 uart0_rx aa14 ae16 internal peripheral 38 uart0_tx u8 af3 internal peripheral 38 uart1_cts /uart1_dsr n8 ac3 internal peripheral 38 uart1_dsr /uart1_cts n8 ac3 internal peripheral 38 uart1_dtr /uart1_rts n7 ad2 internal peripheral 38 signals listed alphabetically (part 9 of 10) signal name 413-ball 456-ball interface group page .com .com .com .com 4 .com u datasheet powerpc 405gp embedded processor data sheet 6/20/03 page 25 of 60 uart1_rts /uart1_dtr n7 ad2 internal peripheral 38 uart1_rx w4 ac1 internal peripheral 38 uart1_tx n3 ac2 internal peripheral 38 uartserclk y14 ae17 internal peripheral 38 v dd a13 d12 d13 k9 k15 l9 l10 l14 l15 l20 m10 m14 n4 n9 n10 n14 n15 p9 p15 y11 y12 ac11 e10 e11 e12 e15 e16 e17 k5 k22 l5 l22 m5 m22 r5 r22 t5 t22 u5 u22 ab10 ab11 ab12 ab15 ab16 ab17 logic voltage 41 we ab16 ac16 sdram 36 signals listed alphabetically (part 10 of 10) signal name 413-ball 456-ball interface group page .com .com .com .com 4 .com u datasheet powerpc 405gp embedded processor data sheet page 26 of 60 6/20/03 signals listed by ball assignment413-ball package (part 1 of 3) ball signal name ball signal name ball signal name ball signal name a1 gnd b17 pciad0 d10 percs5 [gpio14] g13 pciint [perwe ] a2 peraddr4 b18 pciad3 d11 ov dd g15 ov dd a3 peraddr11 b19 reserved d12 v dd g16 pcireq3 a4 peraddr15 b20 pcireq2 d13 v dd g17 drvrinh2 a5 peraddr18 b21 pcireq1 d14 gnd g20 pciserr a6 gnd b22 pciad11 d15 pcireq0 [gnt ] g21 pcireq5 a7 peraddr21 b23 pcignt2 d16 pcic0[be0 ]g22 pciad16 a8 dmaack3 c1 perpar3 d17 pciclk g23 pciad18 a9 peraddr25 c2 eot0/tc0 d18 reserved h1 perdata16 a10 peraddr27 c3 peraddr3 d19 pciad9 h2 perdata22 a11 ov dd c4 peraddr5 d20 pciad12 h3 reserved a12 peraddr28 c5 peraddr8 d21 pciad15 h4 perdata31 a13 v dd c6 dmareq3 d22 pciperr h7 perr/w a14 peraddr29 c7 percs4 [gpio13] d23 pcignt3 h8 pererr a15 dmaack2 c8 peraddr16 e1 perdata24 h9 ov dd a16 dmareq1 c9 peraddr17 e2 reserved h10 ov dd a17 dmaack0 c10 percs7 [gpio16] e3 perpar2 h11 percs1 [gpio10] a18 gnd c11 peraddr2 e4 perw be3 h13 pciad13 a19 pciad4 c12 peraddr24 e20 testen h14 ov dd a20 gpio1[ts1e] c13 dmareq0 e21 pciparity h15 ov dd a21 gpio3[ts1o] c14 gnd e22 pciirdy h16 sysclk a22 pciad10 c15 pciad5 e23 pcic2[be2 ] h17 drvrinh1 a23 gnd c16 reserved f1 gnd h20 pcidevsel b1 perwbe2 c17 pciad6 f2 perdata23 h21 pciframe b2 perwbe1 c18 pciad7 f3 perdata29 h22 pciad17 b3 peraddr6 c19 gpio2[ts2e] f4 perpar1 h23 pcignt5 b4 peraddr9 c20 pciad8 f20 pcireq4 j1 perdata13 b5 peraddr14 c21 phytxclk f21 pcitrdy j2 perdata21 b6 percs6 [gpio15] c22 pcic1[be1 ] f22 emctxd0 j3 perdata25 b7 peraddr19 c23 pcistop f23 gnd j4 perdata28 b8 peraddr20 d1 perdata27 g1 perdata19 j7 ov dd b9 dmareq2 d2 perdata30 g2 perdata20 j8 ov dd b10 peraddr22 d3 perblast g3 perdata26 j9 perclk b11 peraddr23 d4 perwbe0 g4 eot1/tc1 j10 ov dd b12 peraddr26 d5 percs3 [gpio12] g7 peraddr0 j11 gnd b13 peraddr30 d6 peraddr7 g8 percs2 [gpio11] j12 peraddr1 b14 dmaack1 d7 peraddr10 g10 ov dd j13 gnd b15 pciad1 d8 peraddr12 g11 percs0 j14 ov dd b16 pciad2 d9 peraddr13 g12 peraddr31 j15 sysreset .com .com .com .com 4 .com u datasheet powerpc 405gp embedded processor data sheet 6/20/03 page 27 of 60 j16 ov dd l20 v dd n22 pciad24 t1 busreq j17 ov dd l21 av dd n23 gnd t2 perdata3 j20 emcmdclk l22 pciad19 p1 perdata10 t3 memdata31 j21 emctxenl23 ov dd p2 perdata5 t4 memdata27 j22 emctxd2 m1 perdata11 p3 holdpri t7 gpio9[trcclk] j23 pciad21 m2 perdata9 p4 holdack t8 uart0_dtr k1 perdata12 m3 perdata7 p8 ov dd t9 ov dd k2 perdata17 m4 gnd p9 v dd t10 ov dd k3 ov dd m8 perdata15 p10 uart0_dsr t11 memdata17 k4 ov dd m9 memdata20 p11 gnd t13 tdo k8 ov dd m10 v dd p12 gnd t14 ov dd k9 v dd m11 gnd p13 gnd t15 ov dd k10 peroe m12 gnd p14 syserr t16 trst k11 gnd m13 gnd p15 v dd t17 emcmdio [phymdio] k12 gnd m14 v dd p16 ov dd t20 phycrs k13 gnd m15 pciad14 p20 ov dd t21 reserved k14 pcireset m16 pciad25 p21 ov dd t22 phyrxerr k15 v dd m20 gnd p22 pciad27 t23 pciad26 k16 ov dd m21 pciad20 p23 pcic3[be3 ]u1 perdata4 k20 emctxerr m22 pciad22 r1 perdata8 u2 perdata2 k21 emctxd1 m23 pciidsel r2 extreset u3 eot2/tc2 k22 pcignt4 n1 ov dd r3 perdata0 u4 extack k23 pciad23 n2 perdata6 r4 memdata28 u7 uart0_cts l1 gnd n3 uart1_tx r7 ov dd u8 uart0_tx l2 perdata14 n4 v dd r8 ov dd u9 ov dd l3 perdata18 n7 uart1_rts / uart1_dtr r9 memdata19 u11 memdata18 l4 gnd n8 uart1_dsr / uart1_cts r10 ov dd u12 dqm0 l7 perpar0 n9 v dd r11 gnd u13 tdi l8 perready n10 v dd r12 ras u14 ov dd l9 v dd n11 gnd r13 gnd u16 tck l10 v dd n12 gnd r14 ov dd u17 tms l11 gnd n13 gnd r15 cas u20 irq5[gpio22] l12 gnd n14 v dd r16 ov dd u21 irq0[gpio17] l13 gnd n15 v dd r17 ov dd u22 pciad29 l14 v dd n16 ba0 r20 irq2[gpio19] u23 pcignt1 l15 v dd n17 ba1 r21 phyrxdv v1 gnd l16 tmrclk n20 gnd r22 pciad30 v2 holdreq l17 rcvrinh n21 pciad28 r23 emctxd3 v3 eot3/tc3 signals listed by ball assignment413-ball package (part 2 of 3) ball signal name ball signal name ball signal name ball signal name .com .com .com .com 4 .com u datasheet powerpc 405gp embedded processor data sheet page 28 of 60 6/20/03 v4 extreq y15 memaddr8 aa19 memaddr4 ab23 memclkout1 v20 reserved y16 memaddr7 aa20 memaddr2 ac1 gnd v21 reserved y17 phyrxd3 aa21 memaddr0 ac2 dqm2 v22 pciad31 y18 phyrxd2 aa22 irq6[gpio23] ac3 gpio7[ts5] v23 gnd y19 phyrxd1 aa23 halt ac4 gpio5[ts3] w1 perdata1 y20 clken1 ab1 memdata22 ac5 dqm1 w2 memdata29 y21 phycol ab2 memdata15 ac6 gnd w3 memdata24 y22 irq3[gpio20] ab3 iicscl ac7 memdata3 w4 uart1_rx y23 irq1[gpio18] ab4 gpio6[ts4] ac8 memdata0 w20 memclkout0 aa1 memdata26 ab5 reserved ac9 ecc6 w21 irq4[gpio21] aa2 dqm3 ab6 memdata7 ac10 ecc5 w22 reserved aa3 memdata21 ab7 memdata4 ac11 v dd w23 pcignt0 [req ] aa4 memdata14 ab8 memdata6 ac12 ecc4 y1 memdata30 aa5 memdata13 ab9 memdata5 ac13 ov dd y2 memdata25 aa6 memdata11 ab10 memdata1 ac14 ecc3 y3 memdata23 aa7 memdata9 ab11 ecc7 ac15 ecc1 y4 memdata16 aa8 reserved ab12 ecc2 ac16 uart0_ri y5 reserved aa9 memdata8 ab13 dqmcb ac17 banksel2 y6 gpio8[ts6] aa10 gnd ab14 banksel3 ac18 gnd y7 iicsda aa11 memdata2 ab15 uart0_rts ac19 banksel0 y8 memdata12 aa12 ecc0 ab16 we ac20 memaddr10 y9 memdata10 aa13 phyrxd0 ab17 banksel1 ac21 memaddr6 y10 gnd aa14 uart0_rx ab18 gpio4[ts2o] ac22 memaddr1 y11 v dd aa15 memaddr12 ab19 memaddr9 ac23 gnd y12 v dd aa16 memaddr11 ab20 memaddr5 y13 ov dd aa17 uart0_dcd ab21 memaddr3 y14 uartserclk aa18 phyrxclk ab22 clken0 signals listed by ball assignment413-ball package (part 3 of 3) ball signal name ball signal name ball signal name ball signal name .com .com .com .com 4 .com u datasheet powerpc 405gp embedded processor data sheet 6/20/03 page 29 of 60 signals listed by ball assignment456-ball package (part 1 of 3) ball signal name ball signal name ball signal name ball signal name a1 gnd b14 dmaack2 d1 perw be3 e14 gnd a2 gnd b15 dmaack1 d2 perwbe0 e15 v dd a3 peraddr1 b16 pciad1 d3 perpar0 e16 v dd a4 percs3 [gpio12] b17 res C 27/ov dd C 35 d4 gnd e17 v dd a5 peraddr8 b18 pciad6 d5 peraddr0 e18 gnd a6 gnd b19 pcireq2 d6 peraddr4 e19 ov dd a7 dmareq3 b20 pciclk d7 peraddr7 e20 ov dd a8 peraddr15 b21 pciad8 d8 peraddr11 e21 ov dd a9 percs6 [gpio15] b22 pciad11 d9 peraddr14 e22 gnd a10 peraddr19 b23 pciad12 d10 peraddr17 e23 drvrinh2 a11 gnd b24 pcireset d11 peraddr20 e24 drvrinh1 a12 peraddr25 b25 gnd d12 peraddr23 e25 phytxclk a13 peraddr26 b26 gnd d13 peraddr22 e26 pciparity a14 peraddr28 c1 perr/w d14 dmareq1 f1 gnd a15 peraddr29 c2 peroe d15 peraddr31 f2 perblast a16 gnd c3 gnd d16 dmaack0 f3 eot0/tc0 a17 pciad0 c4 percs1 [gpio10] d17 pciad4 f4 perwbe2 a18 pciad3 c5 percs2 [gpio11] d18 gpio1[ts1e] f5 ov dd a19 res C 27/gnd C 35 c6 peraddr6 d19 pcic0[be0 ]f22 ov dd a20 pciad7 c7 peraddr10 d20 reserved f23 pcignt2 a21 gnd c8 peraddr13 d21 pciad10 f24 pcic1[be1 ] a22 gpio3[ts1o] c9 peraddr16 d22 sysreset f25 pciad15 a23 pciad9 c10 peraddr18 d23 gnd f26 gnd a24 pcireq3 c11 dmareq2 d24 tmrclk g1 perdata29 a25 sysclk c12 dmaack3 d25 av dd g2 eot1/tc1 a26 gnd c13 res C 27/ov dd C 35 d26 testen g3 perpar2 b1 pererr c14 peraddr27 e1 perpar3 g4 perpar1 b2 gnd c15 peraddr30 e2 perwbe1 g5 ov dd b3 percs0 c16 dmareq0 e3 perready g22 ov dd b4 peraddr2 c17 pciad2 e4 perclk g23 pcireq4 b5 peraddr3 c18 pciad5 e5 gnd g24 pciserr b6 peraddr5 c19 pcireq0 [gnt ]e6 ov dd g25 pciperr b7 peraddr9 c20 gpio2[ts2e] e7 ov dd g26 pcitrdy b8 peraddr12 c21 pcireq1 e8 ov dd h1 res C 27/gnd C 35 b9 percs4 [gpio13] c22 pciad13 e9 gnd h2 perdata30 b10 percs5 [gpio14] c23 pciint [perwe ]e10 v dd h3 perdata28 b11 percs7 [gpio16] c24 gnd e11 v dd h4 perdata31 b12 peraddr21 c25 rcvrinh e12 v dd h5 ov dd b13 peraddr24 c26 pciad14 e13 gnd h22 ov dd .com .com .com .com 4 .com u datasheet powerpc 405gp embedded processor data sheet page 30 of 60 6/20/03 h23 pcistop m1 perdata12 p14 gnd u1 perdata2 h24 emcmdclk m2 perdata17 p15 gnd u2 holdack h25 pcidevsel m3 perdata14 p16 gnd u3 perdata1 h26 pcignt3 m4 perdata15 p22 gnd u4 perdata0 j1 perdata23 m5 v dd p23 pciad26 u5 v dd j2 perdata26 m11 gnd p24 pciad23 u22 v dd j3 perdata25 m12 gnd p25 emctxd3 u23 pcignt0 [req ] j4 perdata27 m13 gnd p26 pciidsel u24 phyrxerr j5 gnd m14 gnd r1 perdata8 u25 res C 27/ov dd C 35 j22 gnd m15 gnd r2 perdata4 u26 pciad29 j23 pciirdy m16 gnd r3 busreq v1 holdreq j24 pciframe m22 v dd r4 perdata6 v2 eot2/tc2 j25 pcireq5 m23 pciad19 r5 v dd v3 memdata31 j26 emctxd0 m24 pcignt5 r11 gnd v4 memdata29 k1 perdata20 m25 pciad18 r12 gnd v5 gnd k2 res C 27/ov dd C 35 m26 pciad21 r13 gnd v22 gnd k3 perdata22 n1 perdata11 r14 gnd v23 irq1[gpio18] k4 perdata24 n2 perdata13 r15 gnd v24 phyrxdv k5 v dd n3 perdata10 r16 gnd v25 irq0[gpio17] k22 v dd n4 perdata16 r22 v dd v26 pciad31 k23 emctxenn5 gnd r23 pciad25 w1 memdata30 k24 pcic2[be2 ] n11 gnd r24 pciad24 w2 memdata27 k25 emctxerr n12 gnd r25 pciad27 w3 memdata28 k26 pciad16 n13 gnd r26 pcic3[be3 ] w4 memdata26 l1 gnd n14 gnd t1 gnd w5 ov dd l2 perdata21 n15 gnd t2 holdpri w22 ov dd l3 perdata18 n16 gnd t3 extreset w23 phycrs l4 perdata19 n22 gnd t4 perdata3 w24 irq2[gpio19] l5 v dd n23 pcignt4 t5 v dd w25 irq3[gpio20] l11 gnd n24 res C 27/ov dd C 35 t11 gnd w26 res C 27/gnd C 35 l12 gnd n25 pciad20 t12 gnd y1 eot3/tc3 l13 gnd n26 pciad22 t13 gnd y2 memdata25 l14 gnd p1 perdata9 t14 gnd y3 extack l15 gnd p2 perdata7 t15 gnd y4 extreq l16 gnd p3 res C 27/ov dd C 35 t16 gnd y5 ov dd l22 v dd p4 perdata5 t22 v dd y22 ov dd l23 pciad17 p5 gnd t23 pcignt1 y23 reserved l24 emctxd2 p11 gnd t24 pciad28 y24 irq4[gpio21] l25 emctxd1 p12 gnd t25 pciad30 y25 irq5[gpio22] l26 gnd p13 gnd t26 gnd y26 reserved signals listed by ball assignment456-ball package (part 2 of 3) ball signal name ball signal name ball signal name ball signal name .com .com .com .com 4 .com u datasheet powerpc 405gp embedded processor data sheet 6/20/03 page 31 of 60 aa1 gnd ab26 halt ad9 memdata8 ae18 uart0_dcd aa2 memdata23 ac1 uart1_rx ad10 memdata6 ae19 memaddr7 aa3 dqm3 ac2 uart1_tx ad11 memdata2 ae20 memaddr5 aa4 memdata22 ac3 uart1_dsr / uart1_cts ad12 ecc7 ae21 memaddr2 aa5 ov dd ac4 gnd ad13 ecc3 ae22 memaddr0 aa22 ov dd ac5 memdata19 ad14 res C 27/ov dd C 35 ae23 phyrxd0 aa23 memclkout1 ac6 dqm2 ad15 uart0_ri ae24 tdi aa24 irq6[gpio23] ac7 gpio8[ts6] ad16 uart0_rts ae25 gnd aa25 phycol ac8 memdata12 ad17 banksel0 ae26 trst aa26 gnd ac9 gpio5[ts3] ad18 memaddr11 af1 gnd ab1 memdata24 ac10 dqm1 ad19 memaddr8 af2 uart0_dtr ab2 memdata21 ac11 memdata3 ad20 phyrxd3 af3 uart0_tx ab3 gpio9[trcclk] ac12 dqm0 ad21 memaddr3 af4 reserved ab4 uart0_cts ac13 memdata0 ad22 tck af5 gpio7[ts5] ab5 gnd ac14 banksel3 ad23 tdo af6 gnd ab6 ov dd ac15 dqmcb ad24 gnd af7 memdata11 ab7 ov dd ac16 we ad25 syserr af8 res C 27/gnd C 35 ab8 ov dd ac17 memaddr12 ad26 emcmdio [phymdio] af9 memdata7 ab9 gnd ac18 memaddr9 ae1 gnd af10 memdata4 ab10 v dd ac19 memaddr6 ae2 gnd af11 gnd ab11 v dd ac20 phyrxd2 ae3 uart0_dsr af12 ecc5 ab12 v dd ac21 memaddr1 ae4 memdata16 af13 ecc4 ab13 gnd ac22 tms ae5 memdata15 af14 ecc2 ab14 gnd ac23 gnd ae6 memdata14 af15 ecc1 ab15 v dd ac24 ba1 ae7 iicsda af16 gnd ab16 v dd ac25 clken1 ae8 gpio6[ts4] af17 banksel1 ab17 v dd ac26 memclkout0 ae9 memdata9 af18 gpio4[ts2o] ab18 gnd ad1 memdata20 ae10 res C 27/ov dd C 35 af19 memaddr10 ab19 ov dd ad2 uart1_rts / uart1_dtr ae11 memdata5 af20 phyrxclk ab20 ov dd ad3 gnd ae12 memdata1 af21 gnd ab21 ov dd ad4 memdata18 ae13 ecc6 af22 memaddr4 ab22 gnd ad5 memdata17 ae14 ecc0 af23 phyrxd1 ab23 cas ad6 iicscl ae15 banksel2 af24 ras ab24 ba0 ad7 memdata13 ae16 uart0_rx af25 gnd ab25 clken0 ad8 memdata10 ae17 uartserclk af26 gnd signals listed by ball assignment456-ball package (part 3 of 3) ball signal name ball signal name ball signal name ball signal name .com .com .com .com 4 .com u datasheet powerpc 405gp embedded processor data sheet page 32 of 60 6/20/03 signal list the following table provides a summary of the number of package pins associated with each functional interface group. multiplexed pins in the table signal functional description on page 34, each external signal is listed along with a description of the signal function. some signals are multiplexed on the same pin (ball) so that the pin can be used for different functions. multiplexed signals are shown as a default signal with a secondary signal in square brackets (for example, gpio1[ts1e]). active-low signals (for example, ras ) are marked with an overline. it is expected that in any single application a particular pin will always be programmed to serve the same function. the flexibility of multiplexing allows a single chip to offer a richer pin selection than would otherwise be possible. in addition to multiplexing, many pins are also multi-purpose. for example, the ebc peripheral controller address pins are used as outputs by the ppc405gp to broadcast an address to external slave devices when the ppc405gp has control of the external bus. when, during the course of normal chip operation, an external master gains ownership of the external bus, these same pins are used as inputs which are driven by the external master and received by the ebc in the ppc405gp. in this example, the pins are also bidirectional, serving as both inputs and outputs. intialization strapping one group of pins is used as strapped inputs during system reset. these pins function as strapped inputs only during reset and are used for other functions during normal operation (see strapping on page 56). note pin summary group no. of pins 413-ball package 456-ball package 25 mm 35 mm 27mm pci 60 60 60 ethernet 18 18 18 sdram 71 71 71 external peripheral 96 96 96 external master 9 9 9 internal peripheral 15 15 15 interrupts 7 7 7 jtag555 system 19 19 19 total signal pins 300 300 300 ov dd 38 32 24 v dd 22 24 24 gnd 26 60 56 thermal (and gnd) 15 36 36 reserved 12 4 16 total pins 413 456 456 .com .com .com .com 4 .com u datasheet powerpc 405gp embedded processor data sheet 6/20/03 page 33 of 60 that the use of these pins for strapping is not considered multiplexing since the strapping function is not programmable. pull-up and pull-down resistors pull-up and pull-down resistors are used for strapping during reset and to retain unused or undriven inputs in an appropriate state. the recommended pull-up value of 3k ? to +3.3v (10k ? to +5v can be used on 5v tolerant i/os) and pull-down value of 1k ? to gnd, applies only to individually terminated signals. to prevent possible damage to the device, i/os capable of becoming outputs must never be tied together and terminated through a common resistor. if your system-level test methodology permits, input-only signals can be connected together and terminated through either a common resistor or directly to +3.3v or gnd. when a resistor is used, its value must ensure that the grouped i/os reach a valid logic zero or logic one state when accounting for the total input current into the ppc405gp. unused i/os termination of some pins may be necessary when they are unused. although the ppc405gp requires only the pull-up and pull-down terminations as specified in the signal functional description on page 34, good design practice is to terminate all unused inputs or to configure i/os such that they always drive. if unused, the peripheral, sdram, and pci buses should be configured and terminated as follows: ? peripheral interfaceperaddr0:31, perdata0:31, and all of the control signals are driven by default. terminate perready high and pererror low. ? sdramprogram sdram0_cfg[emdulr]=1 and sdram0_cfg[dce]=1. this causes the ppc405gp to actively drive all of the sdram address, data, and control signals. ? pcithe pci pull-up requirements given in the signal functional description apply only when the pci interface is being used. when the pci bridge is unused, configure the pci controller to park on the bus and actively drive pciad31:0, pcic3:0[be3:0 ], and the remaining pci control signals by doing the following: - strap the ppc405gp to disable the internal pci arbiter and to operate the pci interface in synchronous mode. - individually connect pciserr , pciperr , pcitrdy , and pcistop through 3k ? resistors to +3.3v. - terminate pcireq1:5 to +3.3v. - terminate pcireq0 [gnt ] to gnd. external bus control signals all peripheral bus control signals (percs0:7 , perr/w , perwbe0:3 , peroe , perwe , perblast , holdack, extack ) are set to the high-impedance state when extreset =0. in addition, as detailed in the powerpc 405gp embedded processor users manual , the peripheral bus controller can be programmed via ebc0_cfg to float some of these control signals between transactions and/or when an external master owns the peripheral bus. as a result, a pull-up resistor should be added to those control signals where an undriven state may affect any devices receiving that particular signal. the following table lists all of the i/o signals provided by the ppc405gp. please refer to signals listed alphabetically on page 16 for the pin number to which each signal is assigned. .com .com .com .com 4 .com u datasheet powerpc 405gp embedded processor data sheet page 34 of 60 6/20/03 signal functional description (part 1 of 8) multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball. notes: 1. receiver input has hysteresis. 2. must pull up. see pull-up and pull-down resistors on page 33 for recommended termination values. 3. must pull down. see pull-up and pull-down resistors on page 33 for recommended termination values. 4. if not used, must pull up. 5. if not used, must pull down. 6. strapping input during reset; pull up or pull down as required. 7. pull-up may be required. see external bus control signals on page 33. signal name description i/o type notes pci interface pciad31:0 pci address/data bus. multiplexed address and data bus. i/o 5v tolerant 3.3v pci pcic3:0[be3:0 ] pci bus command and byte enables. i/o 5v tolerant 3.3v pci pciparity pci parity. parity is even across pciad0:31 and pcic0:3[be0:3 ]. pciparity is valid one cycle after either an address or data phase. the pci device that drove pciad0:31 is responsible for driving pciparity on the next pci bus clock. i/o 5v tolerant 3.3v pci pciframe pciframe is driven by the current pci bus master to indicate the beginning and duration of a pci access. i/o 5v tolerant 3.3v pci 2 pciirdy pciirdy is driven by the current pci bus master. assertion of pciirdy indicates that the pci initiator is ready to transfer data. i/o 5v tolerant 3.3v pci 2 pcitrdy the target of the current pci transaction drives pcitrdy . assertion of pcitrdy indicates that the pci target is ready to transfer data. i/o 5v tolerant 3.3v pci 2 pcistop the target of the current pci transaction can assert pcistop to indicate to the requesting pci master that it wants to end the current transaction. i/o 5v tolerant 3.3v pci 2 pcidevsel pcidevsel is driven by the target of the current pci transaction. a pci target asserts pcidevsel when it has decoded an address and command encoding and claims the transaction. i/o 5v tolerant 3.3v pci 2 pciidsel pciidsel is used during configuration cycles to select the pci slave interface for configuration. i 5v tolerant 3.3v pci pciserr pciserr is used for reporting address parity errors or catastrophic failures detected by a pci target. i/o 5v tolerant 3.3v pci 2 pciperr pciperr is used for reporting data parity errors on pci transactions. pciperr is driven active by the device receiving pciad0:31, pcic0:3[be0:3 ], and pciparity, two pci clocks following the data in which bad parity is detected. i/o 5v tolerant 3.3v pci 2 pciclk pciclk is used as the asynchronous pci clock when in asynchronous mode. it is unused when the pci interface is operated synchronously with the plb bus. i 5v tolerant 3.3v pci pcireset pci specific reset. o 5v tolerant 3.3v pci pciint [perwe ] pci interrupt. open-drain output (two states; 0 or open circuit) or peripheral write enable. low when any of the four perwbe0:3 write byte enables are low. o 5v tolerant 3.3v pci pcireq0 [gnt ] multipurpose signal, used as pcireq0 when internal arbiter is used, and as gnt when external arbiter is used. i 5v tolerant 3.3v pci .com .com .com .com 4 .com u datasheet powerpc 405gp embedded processor data sheet 6/20/03 page 35 of 60 pcireq1:5 used as pcireq1:5 input when internal arbiter is used. i 5v tolerant 3.3v pci pcignt0 [req ] gnt0 when internal arbiter is used or req when external arbiter is used. o 5v tolerant 3.3v pci pcignt1:5 used as pcignt1:5 output when internal arbiter is used. o 5v tolerant 3.3v pci ethernet interface phyrxd3:0 received data. this is a nibble wide bus from the phy. the data is synchronous with the phyrxclk. i 5v tolerant 3.3v lvttl 1 emctxd3:0 transmit data. a nibble wide data bus towards the net. the data is synchronous to the phytxclk. o 5v tolerant 3.3v lvttl 6 phyrxerr receive error. this signal comes from the phy and is synchronous to the phyrxclk. i 5v tolerant 3.3v lvttl 1 phyrxclk receiver medium clock. this signal is generated by the phy. i 5v tolerant 3.3v lvttl 1 phyrxdv receive data valid. data on the data bus is valid when this signal is activated. deassertion of this signal indicates end of the frame reception. i 5v tolerant 3.3v lvttl 1 phycrs carrier sense signal from the phy. this is an asynchronous signal. i 5v tolerant 3.3v lvttl 1 emctxerr transmit error. this signal is generated by the ethernet controller, is connected to the phy and is synchronous with the phytxclk. it informs the phy that an error was detected. o 5v tolerant 3.3v lvttl 6 emctxen transmit enable. this signal is driven by the emac to the phy. data is valid during the active state of this signal. deassertion of this signal indicates end of frame transmission. this signal is synchronous to the phytxclk. o 5v tolerant 3.3v lvttl 6 phytxclk this clock comes from the phy and is the medium transmit clock. i 5v tolerant 3.3v lvttl 1 phycol collision signal from the phy. this is an asynchronous signal. i 5v tolerant 3.3v lvttl 1 emcmdclk management data clock. the mdclk is sourced to the phy. this clock has a period of 400ns, adjustable via emac0_stacr[opbc]. management information is transferred synchronously with respect to this clock. o 5v tolerant 3.3v lvttl emcmdio[phymdio] management data input/output is a bidirectional signal between the ethernet controller and the phy. it is used to transfer control and status information. i/o 5v tolerant 3.3v lvttl 1 signal functional description (part 2 of 8) multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball. notes: 1. receiver input has hysteresis. 2. must pull up. see pull-up and pull-down resistors on page 33 for recommended termination values. 3. must pull down. see pull-up and pull-down resistors on page 33 for recommended termination values. 4. if not used, must pull up. 5. if not used, must pull down. 6. strapping input during reset; pull up or pull down as required. 7. pull-up may be required. see external bus control signals on page 33. signal name description i/o type notes .com .com .com .com 4 .com u datasheet powerpc 405gp embedded processor data sheet page 36 of 60 6/20/03 sdram interface memdata0:31 memory data bus. notes: 1. memdata0 is the most significant bit (msb). 2. memdata31 is the least significant bit (lsb). i/o 3.3v lvttl memaddr12:0 memory address bus. notes: 1. memaddr12 is the most significant bit (msb). 2. memaddr0 is the least significant bit (lsb). o3.3v lvttl ba1:0 bank address supporting up to 4 internal banks. o 3.3v lvttl ras row address strobe. o 3.3v lvttl cas column address strobe. o 3.3v lvttl dqm0:3 dqm for byte lane: 0 (memdata0:7), 1 (memdata8:15), 2 (memdata16:23), and 3 (memdata24:31) o3.3v lvttl dqmcb dqm for ecc check bits. o 3.3v lvttl ecc0:7 ecc check bits 0:7. i/o 3.3v lvttl banksel0:3 select up to four external sdram banks. o 3.3v lvttl we write enable. o 3.3v lvttl clken0:1 sdram clock enable. o 3.3v lvttl memclkout0:1 two copies of an sdram clock allows, in some cases, glueless sdram attach without requiring this signal to be repowered by a pll or zero-delay buffer. o3.3v lvttl external slave peripheral interface perdata0:31 peripheral data bus used by ppc405gp when not in external master mode, otherwise used by external master. note: perdata0 is the most significant bit (msb) on this bus. i/o 5v tolerant 3.3v lvttl 1 peraddr0:31 peripheral address bus used by ppc405gp when not in external master mode, otherwise used by external master. note: peraddr0 is the most significant bit (msb) on this bus. i/o 5v tolerant 3.3v lvttl 1 perpar0:3 peripheral byte parity signals. i/o 5v tolerant 3.3v lvttl 1 perwbe0:3 as outputs, these pins can act as byte-enables which are valid for an entire cycle or as write-byte-enables which are valid for each byte on each data transfer, allowing partial word transactions. as outputs, pins are used by either the pripheral controller or the dma controller depending upon the type of transfer involved. used as inputs when an external bus master owns the external interface. i/o 5v tolerant 3.3v lvttl 1, 7 signal functional description (part 3 of 8) multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball. notes: 1. receiver input has hysteresis. 2. must pull up. see pull-up and pull-down resistors on page 33 for recommended termination values. 3. must pull down. see pull-up and pull-down resistors on page 33 for recommended termination values. 4. if not used, must pull up. 5. if not used, must pull down. 6. strapping input during reset; pull up or pull down as required. 7. pull-up may be required. see external bus control signals on page 33. signal name description i/o type notes .com .com .com .com 4 .com u datasheet powerpc 405gp embedded processor data sheet 6/20/03 page 37 of 60 [perwe ]pciint peripheral write enable. low when any of the four perwbe0:3 write byte enables are low. or pci interrupt. open-drain output (two states; 0 or open circuit) o 5v tolerant 3.3v pci percs0 peripheral chip select bank 0. o 5v tolerant 3.3v lvttl 7 percs1:7 [gpio10:16] seven additional peripheral chip selects or general purpose i/o. to access this function, software must toggle a dcr bit. o[i/o] 5v tolerant 3.3v lvttl 1, 7 peroe used by either the peripheral controller or the dma controller depending upon the type of transfer involved. when the ppc405gp is the bus master, it enables the selected device to drive the bus. o 5v tolerant 3.3v lvttl 7 perr/w used by the ppc405gp when not in external master mode, as output by either the peripheral controller or dma controller depending upon the type of transfer involved. high indicates a read from memory, low indicates a write to memory. otherwise it used by the external master as an input to indicate the direction of data transfer. i/o 5v tolerant 3.3v lvttl 1 perready used by a peripheral slave to indicate it is ready to transfer data. i 5v tolerant 3.3v lvttl 1 perblast used by the ppc405gp when not in external master mode, otherwise used by external master. indicates the last transfer of a memory access. i/o 5v tolerant 3.3v lvttl 1, 7 dmareq0:3 dmareq0:3 are used by slave peripherals to indicate they are prepared to transfer data. i 5v tolerant 3.3v lvttl 1 dmaack0:3 dmaack0:3 are used by the ppc405gp to cause the dma peripheral to transfer data. o 5v tolerant 3.3v lvttl 6 eot0:3/tc0:3 end of transfer/terminal count. i/o 5v tolerant 3.3v lvttl 1 signal functional description (part 4 of 8) multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball. notes: 1. receiver input has hysteresis. 2. must pull up. see pull-up and pull-down resistors on page 33 for recommended termination values. 3. must pull down. see pull-up and pull-down resistors on page 33 for recommended termination values. 4. if not used, must pull up. 5. if not used, must pull down. 6. strapping input during reset; pull up or pull down as required. 7. pull-up may be required. see external bus control signals on page 33. signal name description i/o type notes .com .com .com .com 4 .com u datasheet powerpc 405gp embedded processor data sheet page 38 of 60 6/20/03 external master peripheral interface perclk peripheral clock to be used by an external master and by synchronous peripheral slaves. o 5v tolerant 3.3v lvttl extreset peripheral reset to be used by an external master and by synchronous peripheral slaves. o 5v tolerant 3.3v lvttl holdreq hold request, used by an external master to request ownership of the peripheral bus. i 5v tolerant 3.3v lvttl 1, 5 holdack hold acknowledge, used by the ppc405gp to transfer ownership of peripheral bus to an external master. o 5v tolerant 3.3v lvttl 6 extreq extreq is used by an external master to indicate it is prepared to transfer data. i 5v tolerant 3.3v lvttl 1 extack extack is used by the ppc405gp to indicate a data transfer cycle. o 5v tolerant 3.3v lvttl 6 holdpri used by an external master to indicate the priority of a given external master tenure. i 5v tolerant 3.3v lvttl 1 busreq used when the ppc405gp needs to regain control of peripheral interface from an external master. o 5v tolerant 3.3v lvttl pererr an input used to indicate to the ppc405gp that an external slave peripheral error occurred. i 5v tolerant 3.3v lvttl 1, 5 internal peripheral interface uartserclk serial clock used to provide an alternate clock to the internally generated serial clock. used in cases where the allowable internally generated baud rates are not satisfactory. this input can be individually connected to either uart. i 5v tolerant 3.3v lvttl 1 uart0_rx uart0 serial data in. i 5v tolerant 3.3v lvttl 1 uart0_tx uart0 serial data out. o 5v tolerant 3.3v lvttl 6 uart0_dcd uart0 data carrier detect. i 5v tolerant 3.3v lvttl 1 uart0_dsr uart0 data set ready. i 5v tolerant 3.3v lvttl 1 uart0_cts uart0 clear to send. i 5v tolerant 3.3v lvttl 1 uart0_dtr uart0 data terminal ready. o 5v tolerant 3.3v lvttl 6 uart0_rts uart0 request to send. o 5v tolerant 3.3v lvttl 6 uart0_ri uart0 ring indicator. i 5v tolerant 3.3v lvttl 1 signal functional description (part 5 of 8) multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball. notes: 1. receiver input has hysteresis. 2. must pull up. see pull-up and pull-down resistors on page 33 for recommended termination values. 3. must pull down. see pull-up and pull-down resistors on page 33 for recommended termination values. 4. if not used, must pull up. 5. if not used, must pull down. 6. strapping input during reset; pull up or pull down as required. 7. pull-up may be required. see external bus control signals on page 33. signal name description i/o type notes .com .com .com .com 4 .com u datasheet powerpc 405gp embedded processor data sheet 6/20/03 page 39 of 60 uart1_rx uart1 serial data in. i 5v tolerant 3.3v lvttl 1 uart1_tx uart1 serial data out. o 5v tolerant 3.3v lvttl 6 uart1_dsr / uart1_cts uart1 data set ready or uart1 clear to send. to access this function, software must toggle a dcr bit. i 5v tolerant 3.3v lvttl 1 uart1_r ts / uart1_dtr uart1 request to send or uart1 data terminal ready. to access this function, software must toggle a dcr bit. o 5v tolerant 3.3v lvttl 6 iicscl iic serial clock. i/o 5v tolerant 3.3v lvttl 1, 2 iicsda iic serial data. i/o 5v tolerant 3.3v lvttl 1, 2 interrupts interface irq0:6[gpio17:23] interrupt requests or general purpose i/o. to access this function, software must toggle a dcr bit. i[i/o] 5v tolerant 3.3v lvttl 1 jtag interface tdi test data in. i 5v tolerant 3.3v lvttl 1, 4 tms jtag test mode select. i 5v tolerant 3.3v lvttl 1, 4 tdo test data out. o 5v tolerant 3.3v lvttl tck jtag test clock. the frequency of this input can range from dc to 25mhz. i 5v tolerant 3.3v lvttl 1, 4 trst jtag reset. trst must be low at power-on to initialize the jtag controller and for normal operation of the ppc405gp. i 5v tolerant 3.3v lvttl 5 system interface sysclk main system clock input. i 5v tolerant 3.3v lvttl sysreset main system reset. external logic can drive this bidirectional pin low (minimum of 16 cycles) to initiate a system reset. a system reset can also be initiated by software. implemented as an open- drain output (two states; 0 or open circuit). i/o 5v tolerant 3.3v lvttl 1, 2 av dd clean voltage input for the pll. i signal functional description (part 6 of 8) multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball. notes: 1. receiver input has hysteresis. 2. must pull up. see pull-up and pull-down resistors on page 33 for recommended termination values. 3. must pull down. see pull-up and pull-down resistors on page 33 for recommended termination values. 4. if not used, must pull up. 5. if not used, must pull down. 6. strapping input during reset; pull up or pull down as required. 7. pull-up may be required. see external bus control signals on page 33. signal name description i/o type notes .com .com .com .com 4 .com u datasheet powerpc 405gp embedded processor data sheet page 40 of 60 6/20/03 syserr set to 1 when a machine check is generated. o 5v tolerant 3.3v lvttl halt halt from external debugger. i 5v tolerant 3.3v lvttl 1, 2 gpio1[ts1e] gpio2[ts2e] general purpose i/o or even trace execution status. to access this function, software must toggle a dcr bit. i/o[o] 5v tolerant 3.3v lvttl 1, 6 gpio3[ts1o] general purpose i/o or odd trace execution status. to access this function, software must toggle a dcr bit. i/o[o] 5v tolerant 3.3v lvttl 1 gpio4[ts2o] general purpose i/o or odd trace execution status. to access this function, software must toggle a dcr bit. i/o[o] 5v tolerant 3.3v lvttl 1, 6 gpio5:8[ts3:6] general purpose i/o or trace status. to access this function, software must toggle a dcr bit. i/o[o] 5v tolerant 3.3v lvttl 1 gpio9[trcclk] general purpose i/o or trace interface clock. a toggling signal that is always half of the cpu core frequency. to access this function, software must toggle a dcr bit. i/o[o] 5v tolerant 3.3v lvttl 1 testen test enable. used only for manufacturing tests. pull down for normal operation. i 2.5v cmos w/pull-down rcvrinh receiver inhibit. used only for manufacturing tests. pull up for normal operation. i 5v tolerant 3.3v lvttl 2 drvrinh1:2 driver inhibit 1 and 2. used only for manufacturing tests. pull up for normal operation. i 5v tolerant 3.3v lvttl 2 tmrclk an external clock input that can be used to clock the timers in the cpu core. i 5v tolerant 3.3v lvttl 1 trace interface [ts1e]gpio1 [ts2e]gpio2 even trace execution status. to access this function, software must toggle a dcr bit or general purpose i/o. o[i/o] 5v tolerant 3.3v lvttl 1, 6 signal functional description (part 7 of 8) multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball. notes: 1. receiver input has hysteresis. 2. must pull up. see pull-up and pull-down resistors on page 33 for recommended termination values. 3. must pull down. see pull-up and pull-down resistors on page 33 for recommended termination values. 4. if not used, must pull up. 5. if not used, must pull down. 6. strapping input during reset; pull up or pull down as required. 7. pull-up may be required. see external bus control signals on page 33. signal name description i/o type notes .com .com .com .com 4 .com u datasheet powerpc 405gp embedded processor data sheet 6/20/03 page 41 of 60 [ts1o]gpio3 odd trace execution status. to access this function, software must toggle a dcr bit or general purpose i/o. o[i/o] 5v tolerant 3.3v lvttl 1 [ts2o]gpio4 odd trace execution status. to access this function, software must toggle a dcr bit or general purpose i/o. o[i/o] 5v tolerant 3.3v lvttl 1, 6 [ts3:6]gpio5:8 trace status. to access this function, software must toggle a dcr bit or general purpose i/o. o[i/o] 5v tolerant 3.3v lvttl 1 [trcclk]gpio9 trace interface clock. a toggling signal that is always half of the cpu core frequency. to access this function, software must toggle a dcr bit or general purpose i/o. o[i/o] 5v tolerant 3.3v lvttl 1 ground pins gnd ground note: on the 456-ball packages, l11-l16, m11-m16, n11-n16, p11-p16, r11-r16, and t11-t16 are also thermal balls. on the 413-ball package, j11, j13, k11-k13, l11-l13, m11- n13, n11-n13, p11-p13, r11, and r13 are also thermal balls. ov dd pins ov dd output driver voltage3.3v. v dd pins v dd logic voltage2.5v. other pins reserved reservedexcept for y5 (on the 413-ball package) or af4, do not connect signals, voltage, or ground to these pins. y5 (on the 413-ball package) and af4 must be tied to ov dd or gnd. signal functional description (part 8 of 8) multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball. notes: 1. receiver input has hysteresis. 2. must pull up. see pull-up and pull-down resistors on page 33 for recommended termination values. 3. must pull down. see pull-up and pull-down resistors on page 33 for recommended termination values. 4. if not used, must pull up. 5. if not used, must pull down. 6. strapping input during reset; pull up or pull down as required. 7. pull-up may be required. see external bus control signals on page 33. signal name description i/o type notes .com .com .com .com 4 .com u datasheet powerpc 405gp embedded processor data sheet page 42 of 60 6/20/03 absolute maximum ratings the absolute maximum ratings below are stress ratings only. operation at or beyond these maximum ratings can cause permanent damage to the device characteristic symbol value unit supply voltage (internal logic) v dd 0 to +2.7 v supply voltage (i/o interface) ov dd 0 to +3.6 v pll supply voltage av dd 0 to +2.7 v input voltage (2.5v cmos receivers) v in -0.6 to v dd + 0.6 v input voltage (3.3v lvttl receivers) v in -0.6 to ov dd + 0.6 v input voltage (5.0v lvttl receivers) v in -0.6 to ov dd + 2.4 v storage temperature range t stg -55 to +150 c case temperature under bias t c -40 to +120 c note: all specified voltages are with respect to gnd. package thermal specifications the ppc405gp is designed to operate within a case temperature range of -40c to +85c. thermal resistance values for the e-pbga packages in a convection environment are as follows: packagethermal resistance symbol airflow ft/min (m/sec) unit 0 (0) 100 (0.51) 200 (1.02) 35mm, 456-ballsjunction-to-case jc 222c/w 35mm, 456-ballscase-to-ambient 1 ca 14 13 12 c/w 27mm, 456-ballsjunction-to-case jc 222c/w 27mm, 456-ballscase-to-ambient 1 ca 18 16 15 c/w 25mm, 413-ballsjunction-to-case jc 1.5 1.5 1.5 c/w 25mm, 413-ballscase-to-ambient 1 ca 17 15 13 c/w note: 1. for a chip mounted on a jedec 2s2p card without a heat sink. 2. for a chip mounted on a card with at least one signal and two power planes, the following relationships exist: a. case temperature, t c , is measured at top center of case surface with device soldered to circuit board. b. t a = t c C p ca , where t a is ambient temperature and p is power consumption. c. t cmax = t jmax C p jc , where t jmax is maximum junction temperature and p is power consumption. .com .com .com .com 4 .com u datasheet powerpc 405gp embedded processor data sheet 6/20/03 page 43 of 60 recommended dc operating conditions device operation beyond the conditions specified is not recommended. extended operation beyond the recommended conditions can affect device reliability. notes: 1. pci drivers meet pci specifications. parameter symbol minimum typical maximum unit notes logic supply voltage v dd 2.3 2.5 2.7 v i/o supply voltage ov dd 3.0 3.3 3.6 v pll supply voltage av dd 2.3 2.5 2.7 v input logic high (2.5v cmos receivers) v ih 1.7 v dd v input logic high (3.3v lvttl receivers) v ih 2.0 ov dd v input logic high (5.0v lvttl receivers) v ih 2.0 5.0 v input logic low (2.5v cmos receivers) v il 0 0.7 v input logic low (3.3/5.0v lvttl receivers) v il 00.8v output logic high v oh 2.4 ov dd v output logic low v ol 00.4v 3.3v i/o input current (no pull-up or pull-down) i il1 10 a input current (with internal pull-down) i il2 10 (@ 0v) 400 (@ v dd ) a 5v tolerant i/o input current 1 i il4 10 -650 a input max allowable overshoot (2.5v cmos receivers) v imao25 v dd + 0.6 v input max allowable overshoot (3.3v lvttl receivers) v imao3 ov dd + 0.6 v input max allowable overshoot (5.0v lvttl receivers) v imao5 5.5 v input max allowable undershoot v imau -0.6 v output max allowable overshoot v omao ov dd + 0.3 v output max allowable undershoot v omau3 -0.6 v case temperature t c -40 +85 c notes: 1. see 5v-tolerant input current on page 44 .com .com .com .com 4 .com u datasheet powerpc 405gp embedded processor data sheet page 44 of 60 6/20/03 5v-tolerant input current input capacitance parameter symbol maximum unit notes 3.3v lvttl i/o c in1 5.5 pf 5v tolerant lvttl i/o c in2 5pf pci i/o c in3 7pf rx only pins c in4 4pf -700 -600 -500 -400 -300 -200 -100 0 100 1.0 2.0 3.0 4.0 5.0 0.0 input current ( a) input voltage (v) .com .com .com .com 4 .com u datasheet powerpc 405gp embedded processor data sheet 6/20/03 page 45 of 60 dc electrical characteristics parameter symbol minimum typical maximum unit active operating current (v dd )C133mhz i dd tbd tbd ma active operating current (v dd )C200mhz i dd 550 670 ma active operating current (v dd )C266 mhz i dd 730 880 ma active operating current (ov dd )C133mhz i odd tbd tbd ma active operating current (ov dd )C200mhz i odd 35 37 ma active operating current (ov dd )C266 mhz i odd 37 40 ma pll v dd input current i pll 16 23 ma active operating powerC133mhz p dd tbd tbd w active operating powerC200mhz p dd 1.5 2.0 1 w active operating powerC266mhz p dd 2.0 2.6 1 w note: 1. maximum power is characterized at v dd = +2.7v, ov dd = +3.6v, t c = +85 c, across the silicon process (worse case to best case), while running an application designed to maximize power consumption. the specifications at 200mhz correspond to cpu = 200 mhz, plb = 100mhz, opb = ebc = 50mhz, pci = 33.3mhz. the specifications at 266mhz correspond to cpu = 266.6mhz, plb =133.3mhz, opb = ebc = 66.6mhz, and pci = 33.3mhz. 2. av dd should be derived from v dd using the following circuit: v dd c1 c2 c3 av dd l1 l1 C 2.2 h smt inductor (equivalent to murata lqh3c2r2m34) or smt chip ferrite bead (equivalent to murata blm31a700s) c1 C 3.3 f smt tantalum c2 C 0.1 f smt monolithic ceramic capacitor with x7r dielectric or equivalent c3 C 0.01 f smt monolithic ceramic capacitor with x7r dielectric or equivalent + agnd gnd .com .com .com .com 4 .com u datasheet powerpc 405gp embedded processor data sheet page 46 of 60 6/20/03 test conditions clock timing and switching characteristics are specified in accordance with operating conditions shown in the table recommended dc operating conditions. for all signals other than pci signals, ac specifications are characterized at ov dd = +3v and t c = +85c with the 50pf test load shown in the figure at right. for pci signals there are two different test load circuits, one for the rising edge and one the falling edge as shown in the figures at right. output pin 50pf all signals other than pci output pin 10pf 25 ? output pin 10pf 25 ? ov dd pci rising edge pci falling edge .com .com .com .com 4 .com u datasheet powerpc 405gp embedded processor data sheet 6/20/03 page 47 of 60 clocking waveform clocking specifications symbol parameter min max units cpu pf c processor clock frequency 133.33/200/266.66 mhz pt c processor clock period 7.5/5/3.75 ns sysclk input scf c clock input frequency 25 66.66 mhz sct c clock period 15 40 ns sct cs clock edge stability (phase jitter, cycle to cycle) 0.15 ns sct ch clock input high time 40% of nominal period 60% of nominal period ns sct cl clock input low time 40% of nominal period 60% of nominal period ns note: input slew rate > 2v/ns memclkout output mcof c clock output frequency @ pf c = 133mhz 66.66 mhz mcot c clock period @ pf c = 133mhz 15 ns mcof c clock output frequency @ pf c = 200mhz 100 mhz mcot c clock period @ pf c = 200mhz 10 ns mcof c clock output frequency @ pf c = 266mhz 133.33 mhz mcot c clock period @ pf c = 266mhz 7.5 ns mcot cs clock edge stability (phase jitter, cycle to cycle) 0.2 ns mcot ch clock output high time 45% of nominal period 55% of nominal period ns mcot cl clock output low time 45% of nominal period 55% of nominal period ns other clocks vcof c vco frequency 400 800 mhz plbf c plb frequency @ pf c = 133mhz 66.66 mhz plbf c plb frequency @ pf c = 200mhz 100 mhz plbf c plb frequency @ pf c = 266mhz 133.33 mhz opbf c opb frequency @ pf c = 133mhz 33.33 mhz opbf c opb frequency @ pf c = 200mhz 50 mhz opbf c opb frequency @ pf c = 266mhz 66.66 mhz t cl t ch t c 2.0v 1.5v 0.8v .com .com .com .com 4 .com u datasheet powerpc 405gp embedded processor data sheet page 48 of 60 6/20/03 spread spectrum clocking care must be taken when using a spread spectrum clock generator (sscg) with the ppc405gp. this controller uses a pll for clock generation inside the chip. the accuracy with which the pll follows the sscg is referred to as tracking skew. the pll bandwidth and phase angle determine how much tracking skew there is between the sscg and the pll for a given frequency deviation and modulation frequency. when using an sscg with the ppc405gp the following conditions must be met: ? the frequency deviation must not violate the minimum clock cycle time. therefore, when operating the ppc405gp with one or more internal clocks at their maximum supported frequency, the sscg can only lower the frequency. ? the maximum frequency deviation cannot exceed ? 3%, and the modulation frequency cannot exceed 40khz. in some cases, on-board ppc405gp peripherals impose more stringent requirements (see note 1). ? use the peripheral bus clock (perclk) for logic that is synchronous to the peripheral bus since this clock tracks the modulation. ? use the sdram memclkout since it also tracks the modulation. please refer to the application note using a spread spectrum clock generator with the powerpc 405gp for additional details. this application note is available on the ibm microelectronics web site at http://www.chips.ibm.com. notes: 1. the serial port baud rates are synchronous to the modulated clock. the serial port has a tolerance of approximately 1.5% on baud rate before framing errors begin to occur. the 1.5% tolerance assumes that the connected device is running at precise baud rates. if an external serial clock is used the baud rate is unaffected by the modulation. 2. operation of the ppc405gp pci bridge is unaffected by the use of a sscg. for pci frequencies of 33.33 mhz and below the pci controller supports synchronous mode operation. this is accomplished by strapping the ppc405gp for synchronous mode pci and connecting the pci bus clock to the ppc405gp sysclk input. for 33.33 mhz signalling, the pci specification has no limitation on the amount of frequency deviation or modulation that may be applied to the pci clock. therefore, the ppc405gp sscg requirements stated above take precedence. at pci frequencies above 33.33 mhz, the pci controller must be operated in asynchronous mode. when in asynchronous mode, the pci bus clock must be driven into the ppc405gp pciclk input. in this configuration the pci controller supports the 66.66 mhz pci clock specification which specifies a maximum frequency deviation of -1% at a modulation of between 30 khz and 33 khz. 3. ethernet operation is unaffected. 4. iic operation is unaffected. caution: it is up to the system designer to ensure that any sscg used with the ppc405gp meets the above requirements and does not adversely affect other aspects of the system. .com .com .com .com 4 .com u datasheet powerpc 405gp embedded processor data sheet 6/20/03 page 49 of 60 peripheral interface clock timings parameter min max units pciclk input frequency (asynchronous mode) note 1 66.66 mhz pciclk period (asynchronous mode) 15 note 1 ns pci clock frequency (synchronous mode) 25 33.33 mhz pci clock period (synchronous mode - note 2) 30 40 ns pciclk input high time 40% of nominal period 60% of nominal period ns pciclk input low time 40% of nominal period 60% of nominal period ns emcmdclk output frequency C 2.5 mhz emcmdclk period 400 C ns emcmdclk output high time 160 C ns emcmdclk output low time 160 C ns phytxclk input frequency 2.5 25 mhz phytxclk period 40 400 ns phytxclk input high time 35% of nominal period C ns phytxclk input low time 35% of nominal period C ns phyrxclk input frequency 2.5 25 mhz phyrxclk period 40 400 ns phyrxclk input high time 35% of nominal period C ns phyrxclk input low time 35% of nominal period C ns perclk output frequencyC133mhz C 33.33 mhz perclk periodC133mhz 30 C ns perclk output frequencyC200mhz C 50 mhz perclk periodC200mhz 20 C ns perclk output frequencyC266mhz C 66.66 mhz perclk periodC266mhz 15 C ns perclk output high time 45% of nominal period 55% of nominal period ns perclk output low time 45% of nominal period 55% of nominal period ns perclk clock edge stability (phase jitter, cycle to cycle) 0.3 ns uartserclk input frequency (note 3) C 1000/(2t opb +2ns) mhz uartserclk period 2t opb +2 Cns uartserclk input high time t opb +1 Cns uartserclk input low time t opb +1 Cns tmrclk input frequencyC133mhz C 33.33 mhz tmrclk periodC133mhz 30 C ns tmrclk input frequencyC200mhz C 50 mhz tmrclk periodC200mhz 20 C ns tmrclk input frequencyC266mhz C 66.66 mhz tmrclk periodC266mhz 15 C ns .com .com .com .com 4 .com u datasheet powerpc 405gp embedded processor data sheet page 50 of 60 6/20/03 input setup and hold waveform output delay and float timing waveform tmrclk input high time 40% of nominal period 60% of nominal period ns tmrclk input low time 40% of nominal period 60% of nominal period ns note: 1. in asynchronous pci mode the minimum pciclk frequency is 1/8 the plb clock. refer to the powerpc 405gp embedded processor users manual for more information. 2. in synchronous pci mode the pci clock is derived from sysclk and the pciclk input pin is unused. 3. t opb is the period in ns of the opb clock. the maximum opb clock frequency is 50 mhz for 200mhz parts and 66.66mhz for 266mhz parts. peripheral interface clock timings (continued) parameter min max units clock t is t ih min min inputs valid valid clock outputs valid t oh min t ov max t ov max t oh min t ov max t oh min float (high-z) high (drive) low (drive) .com .com .com .com 4 .com u datasheet powerpc 405gp embedded processor data sheet 6/20/03 page 51 of 60 notes: 1. in all of the following i/o specifications tables a timing values of na means not applicable and dc means dont care. 2. see test conditions on page 46 for output capacitive loading. i/o specificationsall speeds (part 1 of 3) notes: 1. pci timings are for operation up to 66.66mhz. pci output hold time requirement is 1ns for 66.66mhz and 2ns for 33.33mhz. in synchronous mode, timing is relative to sysclk. in asynchronous mode, timing is relative to pciclk. 2. ethernet interface meets timing requirements as defined by ieee 802.3 standard. 3. for pci, i/o h is specified at 0.9ov dd and i/o l is specified at 0.1ov dd . for all other interfaces, i/o h is specified at 2.4 v and i/o l is specified at 0.4 v. signal input (ns) output (ns) output current (ma) clock notes setup time (t is min) hold time (t ih min) valid delay (t ov max) hold time (t oh min) i/o h (min) i/o l (min) pci interface pciad31:0 3 0 6 1 0.5 1.5 pci clock 1 pcic3:0[be 3:0 ] 3 0 6 1 0.5 1.5 pci clock 1 pciclk dc dc na na na na async pcidevsel 3 0 6 1 0.5 1.5 pci clock 1 pciframe 3 0 6 1 0.5 1.5 pci clock 1 pcignt0 [req ] pcignt1:5 na na 6 1 0.5 1.5 pci clock 1 pciidsel 3 0 6 1 na na pci clock 1 pciint [perwe ] na na dc dc 0.5 1.5 pci clock async pciirdy 3 0 6 1 0.5 1.5 pci clock 1 pciparity 3 0 6 1 0.5 1.5 pci clock 1 pciperr 3 0 6 1 0.5 1.5 pci clock 1 pcireq0 [gnt ] pcireq1:5 5 0 na na na na pci clock 1 pcireset na na na na 0.5 1.5 pci clock pciserr na na na na 0.5 1.5 pci clock pcistop 3 0 6 1 0.5 1.5 pci clock 1 pcitrdy 3 0 6 1 0.5 1.5 pci clock 1 ethernet interface emcmdclk na na settable 2 9 6 2, async emcmdio[phymdio] 100 0 1 opb clock period + 10ns 1 opb clock period 9 6 emcmdclk 2 emctxd3:0 na na 20 2 9 6 phytx 2 emctxen na na 20 2 9 6 phytx 2 emctxerr na na 20 2 9 6 phytx 2 phycol 9 6 2, async phycrs 9 6 2, async phyrxclk na na 2, async phyrxd3:0 4 1 na na 9 6 phyrx 2 phyrxdv 4 1 na na 9 6 phyrx 2 phyrxerr 4 1 na na 9 6 phyrx 2 phytxclk na na 2, async .com .com .com .com 4 .com u datasheet powerpc 405gp embedded processor data sheet page 52 of 60 6/20/03 internal peripheral interface iicscl na na na na 19 12 iicsda na na na na 19 12 uart0_cts nana 12 8 uart0_dcd nana 12 8 uart0_dsr nana 12 8 uart0_dtr 12 8 uart0_ri nana 12 8 uart0_rts nana12 8 uart0_rx na na 12 8 uart0_tx na na 12 8 uart1_rts / uart1_dtr nana12 8 uart1_dsr / uart1_cts nana na na uart1_rx na na na na uart1_tx na na 12 8 uartserclk na na na na interrupts interface irq0:6[gpio17:23] 12 8 jtag interface tck na na async tdi na na async tdo 12 8 async tms na na async trst na na async i/o specificationsall speeds (part 2 of 3) notes: 1. pci timings are for operation up to 66.66mhz. pci output hold time requirement is 1ns for 66.66mhz and 2ns for 33.33mhz. in synchronous mode, timing is relative to sysclk. in asynchronous mode, timing is relative to pciclk. 2. ethernet interface meets timing requirements as defined by ieee 802.3 standard. 3. for pci, i/o h is specified at 0.9ov dd and i/o l is specified at 0.1ov dd . for all other interfaces, i/o h is specified at 2.4 v and i/o l is specified at 0.4 v. signal input (ns) output (ns) output current (ma) clock notes setup time (t is min) hold time (t ih min) valid delay (t ov max) hold time (t oh min) i/o h (min) i/o l (min) .com .com .com .com 4 .com u datasheet powerpc 405gp embedded processor data sheet 6/20/03 page 53 of 60 system interface drvrinh1:2 dcdcnananana gpio1[ts1e] gpio2[ts2e] gpio3[ts1o] gpio4[ts2o] gpio5[ts3] gpio6[ts4] gpio7[ts5] gpio8[ts6] gpio9[trcclk] 12 8 halt dc dc na na na na async rcvrinh dcdcnananana sysclk nananana syserr na na 12 8 async sysreset 101128 async testen dc dc na na na na async tmrclk dc dc na na na na async i/o specificationsall speeds (part 3 of 3) notes: 1. pci timings are for operation up to 66.66mhz. pci output hold time requirement is 1ns for 66.66mhz and 2ns for 33.33mhz. in synchronous mode, timing is relative to sysclk. in asynchronous mode, timing is relative to pciclk. 2. ethernet interface meets timing requirements as defined by ieee 802.3 standard. 3. for pci, i/o h is specified at 0.9ov dd and i/o l is specified at 0.1ov dd . for all other interfaces, i/o h is specified at 2.4 v and i/o l is specified at 0.4 v. signal input (ns) output (ns) output current (ma) clock notes setup time (t is min) hold time (t ih min) valid delay (t ov max) hold time (t oh min) i/o h (min) i/o l (min) .com .com .com .com 4 .com u datasheet powerpc 405gp embedded processor data sheet page 54 of 60 6/20/03 i/o specifications133 and 200mhz notes: 1. the sdram command interface is configurable through sdram0_tr[ldf] to provide a 2 to 4 cycle delay before the command is used by sdram. 2. sdram i/o timings are specified relative to a memclkout terminated into a lumped 10pf load. 3. sdram interface hold times are guaranteed at the ppc405gp package pin. system designers must use the ppc405gp ibis model (available from www.chips.ibm.com ) to ensure their clock distribution topology minimizes loading and reflections, and that the relative delays on clock wiring do not exceed the delays on other sdram signal wiring. 4. perclk rising edge at package pin with a 10pf load trails the internal plb clock by approximately 0.8ns. 5. i/o h is specified at 2.4 v and i/o l is specified at 0.4 v. signal input (ns) output (ns) output current (ma) clock notes setup time (t is min) hold time (t ih min) valid delay (t ov max) hold time (t oh min) i/o h (minimum) i/o l (minimum) sdram interface ba1:0 na na 7.5 1 19 12 memclkout 1, 2 banksel 3:0 na na 6.2 1 19 12 memclkout 2 cas na na 7.5 1 19 12 memclkout 1, 2 clken0:1 na na 5.2 1 40 25 memclkout 2 dqm0:3 na na 6.1 1 19 12 memclkout 2 dqmcb na na 6.2 1 19 12 memclkout 2 ecc0:7 2 1 6.2 1 19 12 memclkout 2 memaddr12:0 na na 7.6 1 19 12 memclkout 1, 2 memdata0:31 2 1 6.3 1 19 12 memclkout 2 ras na na 7.5 1 19 12 memclkout 1, 2 we na na 7.5 1 19 12 memclkout 1, 2 external slave peripheral interface dmaack0:3 na na 8 0 12 8 perclk dmareq0:3 5 1 na na na na perclk eot0:3/tc0:3 dc dc 8 0 12 8 perclk peraddr0:31 4 1 10 0 19 12 perclk perblast 4 1 8 0 12 8 perclk percs0 percs1:7 [gpio10:16] nana8 0128perclk perdata0:31 6 1 10 0 19 12 perclk peroe nana8 0128perclk perpar0:3 4 1 10 0 19 12 perclk perr/w 4 1 8 0 12 8 perclk perready 9 1 na na na na perclk perwbe0:3 3 1 8 0 12 8 perclk external master peripheral interface busreq nana8 0128perclk extack nana7 0128perclk extreq 5 1nanananaperclk extreset na na 8 0 19 12 perclk holdack na na 8 0 12 8 perclk holdpri 4 1 na na na na perclk holdreq 5 1 na na na na perclk perclk na na 0.9 0.7 19 12 plb clk 4 pererr 3 1 na na na na perclk .com .com .com .com 4 .com u datasheet powerpc 405gp embedded processor data sheet 6/20/03 page 55 of 60 i/o specifications266mhz notes: 1. the sdram command interface is configurable through sdram0_tr[ldf] to provide a 2 to 4 cycle delay before the command is used by sdram. 2. sdram i/o timings are specified relative to a memclkout terminated into a lumped 10pf load. 3. sdram interface hold times are guaranteed at the ppc405gp package pin. system designers must use the ppc405gp ibis model (available from www.chips.ibm.com ) to ensure their clock distribution topology minimizes loading and reflections, and that the relative delays on clock wiring do not exceed the delays on other sdram signal wiring. 4. perclk rising edge at package pin with a 10pf load trails the internal plb clock by approximately 0.8ns. 5. i/o h is specified at 2.4 v and i/o l is specified at 0.4 v. signal input (ns) output (ns) output current (ma) clock notes setup time (t is min) hold time (t ih min) valid delay (t ov max) hold time (t oh min) i/o h (maximum) i/o l (minimum) sdram interface ba1:0 na na 5.7 1 19 12 memclkout 1, 2 banksel3:0 na na 4.8 1 19 12 memclkout 2 cas na na 5.7 1 19 12 memclkout 1, 2 clken0:1 na na 4.2 1 40 25 memclkout 2 dqm0:3 na na 4.8 1 19 12 memclkout 2 dqmcb na na 4.8 1 19 12 memclkout 2 ecc0:7 1.5 1 4.8 1 19 12 memclkout 2 memaddr12:0 na na 5.7 1 19 12 memclkout 1, 2 memdata0:31 1.5 1 4.9 1 19 12 memclkout 2 ras na na 5.7 1 19 12 memclkout 1, 2 we na na 5.7 1 19 12 memclkout 1, 2 external slave peripheral interface dmaack0:3 na na 6 0 12 8 perclk dmareq0:3 4 1 na na na na perclk eot0:3/tc0:3 dc dc 6 0 12 8 perclk peraddr0:31 3 1 7.2 0 19 12 perclk perblast 3 1 6 0 12 8 perclk percs0 percs1:7 [gpio10:16] nana6 0128perclk perdata0:31 5 1 7.2 0 19 12 perclk peroe nana6 0128perclk perpar0:3 3 1 7.2 0 19 12 perclk perr/w 4 1 6 0 12 8 perclk perready 6.5 1 na na na na perclk perwbe0:3 3 1 6 0 12 8 perclk external master peripheral interface busreq nana6 0128perclk extack nana6 0128perclk extreq 41nanananaperclk extreset na na 6 0 19 12 perclk holdack na na 6 0 12 8 perclk holdpri 3 1 na na na na perclk holdreq 4 1 na na na na perclk perclk na na 0.9 0.7 19 12 plb clk 4 pererr 3 1 na na na na perclk .com .com .com .com 4 .com u datasheet powerpc 405gp embedded processor data sheet page 56 of 60 6/20/03 strapping when the sysreset input is driven low by an external device (system reset), the state of certain i/o pins is read to enable default initial conditions prior to ppc405gp start-up. the actual capture instant is the nearest sysclk edge before the deassertion of reset. these pins must be strapped using external pull-up (logical 1) or pull-down (logical 0) resistors to select the desired default conditions. the recommended pull-up is 3k ? to +3.3v or 10k ? to +5v. the recommended pull-down is 1k ? to gnd. these pins are use for strap functions only during reset. they are used for other signals during normal operation. the following table lists the strapping pins along with their functions and strapping options. the pin for the 456-ball package is listed first (for example, af3), followed by the corresponding pin for the 413-ball package (for example, u8), which appears as af3/u8. the signal names assigned to the pins for normal operation follow the pin numbers. ppc405gp strapping pin assignments (part 1 of 2) function option ball strapping pll tuning 1 for 6 m 7 use choice 3 for 7 < m 12 use choice 5 for 12 < m 32 use choice 6 af3/u8 uart0_tx af2/t8 uart0_dtr ad16/ab15 uart0_rts choice 1; tune[5:0] = 010001 0 0 0 choice 2; tune[5:0] = 111011 0 0 1 choice 3; tune[5:0] = 010011 0 1 0 choice 4; tune[5:0] = 111101 0 1 1 choice 5; tune[5:0] = 010101 1 0 0 choice 6; tune[5:0] = 010110 1 0 1 choice 7; tune[5:0] = 111110 1 1 0 choice 8; tune[5:0] = 100100 1 1 1 pll forward divider 2 d16/a17 dmaack0 b15/b14 dmaack1 bypass mode 0 0 divide by 3 0 1 divide by 4 1 0 divide by 6 1 1 pll feedback divider 2 b14/a15 dmaack2 c12/a8 dmaack3 divide by 1 0 0 divide by 2 0 1 divide by 3 1 0 divide by 4 1 1 plb divider from cpu 2 p25/r23 emctxd3 l24/j22 emctxd2 divide by 1 0 0 divide by 2 0 1 divide by 3 1 0 divide by 4 1 1 opb divider from plb 2 l25/k21 emctxd1 j26/f22 emctxd0 divide by 1 0 0 divide by 2 0 1 divide by 3 1 0 divide by 4 1 1 .com .com .com .com 4 .com u datasheet powerpc 405gp embedded processor data sheet 6/20/03 page 57 of 60 pci divider from plb 2, 3 d18/a20 gpio1[ts1e] c20/c19 gpio2[ts2e] divide by 1 0 0 divide by 2 0 1 divide by 3 1 0 divide by 4 1 1 external bus divider from plb 2 k25/k20 emctxerr k23/j21 emctxen divide by 2 0 0 divide by 3 0 1 divide by 4 1 0 divide by 5 1 1 rom width ac2/n3 uart1_tx ad2/n7 uart1_rts / uart1_dtr 8-bit rom 0 0 16-bit rom 0 1 32-bit rom 1 0 reserved 1 1 rom location u2/p4 holdack ppc405gp peripheral attach 0 ppc405gp pci attach 1 pci asynchronous mode enable y3/u4 extack synchronous pci mode 0 asynchronous mode 1 pci arbiter enable 3 af18/ab18 gpio4[ts2o] internal arbiter disabled 0 internal arbiter enabled 1 note: 1. the tune bits adjust parameters that control pll jitter. the recommended values minimize jitter for the pll implemented in th e ppc405gp. these bits are shown for information only; and do not require modification except in special clocking circumstances such as spread spectrum clocking. for details on the use of spread spectrum clock generators (sscgs) with the ppc405gp, visit the technical documents area of the ibm powerpc web site. 2. not all combinations of dividers produce valid operating configurations. frequencies must be within the limits specified in clocking specifications on page 47. further requirements are detailed in the clocking chapter of the powerpc 405gp embedded processor users manual . 3. additional consideration must be given to pins that normally function as trace signals. improved design margin can be gained by using three-state buffers instead of strapping resistors, and minimizing trace lengths and stubs. ppc405gp strapping pin assignments (part 2 of 2) function option ball strapping .com .com .com .com 4 .com u datasheet powerpc 405gp embedded processor data sheet page 58 of 60 6/20/03 revision log date contents of modification 02/12/2003 timing diagram update 04/14/2003 update legal statements regarding document status. 06/19/2003 add 133 mhz part numbers. .com .com .com .com 4 .com u datasheet powerpc 405gp embedded processor data sheet 6/20/03 page 59 of 60 inside of back cover .com .com .com .com 4 .com u datasheet powerpc 405gp embedded processor data sheet page 60 of 60 6/20/03 ? (c) copyright international business machines corporation 1999, 2003 all rights reserved printed in the united states of america, june 2003 the following are trademarks of international business machines corporation in the united states, or other countries, or both: other company, product, and service names may be trademarks or service marks of others. all information contained in this document is subject to change without notice. the products described in this document are not intended for use in implantation, life support, or other hazardous uses where malfunction could result in death, bodily injury, or catastrophic property damage. the information contained in this document does not affect or change ibm product specifications or warranties. nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of ibm or third parties. all information contained in this document was obtained in specific environments, and is presented as an illustration. the results obtained in other operating environments may vary. the information contained in this document is provided on an "as is" basis. in no event will ibm be liable for damages arising directly or indirectly from any use of the information contained in this document. ibm microelectronics division 1580 route 52 hopewell junction, ny 12533-6351 the ibm home page is www.ibm.com . the ibm microelectronics division home page is www.chips.ibm.com . sa14-2521-13 60 blue logic coreconnect ibm logo codepack ibm powerpc .com .com .com 4 .com u datasheet |
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